Code

Fix Seq Mem Ports #401

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rachitnigam merged 19 commits intomastercucapra/dahlia:masterfrom mem-portscucapra/dahlia:mem-portsCopy head branch name to clipboardMar 8, 2024

+126-83

Commits

Commits on Jul 19, 2023

• fix seq mem ports

  calebmkim

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  1e0181e

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Commits on Feb 16, 2024

• Handle TRecType in areEqual (#404)

  

  Mark1626

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  rachitnigam

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  395d243

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• Update documentation types and views (#406)

  

  Mark1626

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  rachitnigam

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  2091a46

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• BigInt in EInt to allow large literals in let (#409)

  

  Mark1626

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  rachitnigam

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  b7e776d

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• Fix parsing issue of hex numbers in cast expr (#412)

  

  Mark1626

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  rachitnigam

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  2116ed3

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• Fix issue in C++ backend when passing let variable to functions (#414)

  

  Mark1626

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  rachitnigam

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  956acf2

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• @static -> @Promotable

  

  calebmkim

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  rachitnigam

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  0b977eb

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• fix test

  

  calebmkim

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  rachitnigam

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  0e73f0c

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• update scala and sbt versions

  rachitnigam

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  af9d6f5

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• Use new location for Calyx primitives

  rachitnigam

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  f6665ae

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• explicit type

  rachitnigam

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  0fe088f

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• update tests

  rachitnigam

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  4584f53

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• period to docs

  

  calebmkim

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  rachitnigam

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  b8d5483

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• Merge branch 'master' into mem-ports

  rachitnigam

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  0f01db2

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• i hate vscode

  rachitnigam

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  22f4e87

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• dont generate write_en assignment for reads

  rachitnigam

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  88e05e5

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Commits on Mar 6, 2024

• Merge branch 'master' into mem-ports

  rachitnigam

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  345887c

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Commits on Mar 8, 2024

• fix syntax

  rachitnigam

  committed
  eef617c

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• Merge branch 'master' into mem-ports

  rachitnigam

  committed
  019abeb

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