SoCGen is a Verilog RTL Generation and wiring tool which allows fast and fluid development of System-On-Chip Designs by using Yaml-syntaxed description files.
This is still in very early development!!!
Features that will be added:
- Yaml Parsing
- Register/Address Map Generation
- C Header File generation
- Updating of Yaml files by parsing existing RTL
- I/O Pad Generation
- Custom Backend Support
- Connection/Interface Linting and Checking