sync kvm patch for loongarch

Documentation/admin-guide/kernel-parameters.txt

@@ -3939,9 +3939,10 @@
 			vulnerability. System may allow data leaks with this
 			option.
 
-	no-steal-acc	[X86,PV_OPS,ARM64,PPC/PSERIES] Disable paravirtualized
-			steal time accounting. steal time is computed, but
-			won't influence scheduler behaviour
+	no-steal-acc	[X86,PV_OPS,ARM64,PPC/PSERIES,RISCV,LOONGARCH,EARLY]
+			Disable paravirtualized steal time accounting. steal time
+			is computed, but won't influence scheduler behaviour
+
 
 	nosync		[HW,M68K] Disables sync negotiation for all devices.
 

arch/loongarch/Kconfig

@@ -628,6 +628,26 @@ config RANDOMIZE_BASE_MAX_OFFSET
 
 	  This is limited by the size of the lower address memory, 256MB.
 
+config PARAVIRT
+	bool "Enable paravirtualization code"
+	depends on AS_HAS_LVZ_EXTENSION
+	help
+	  This changes the kernel so it can modify itself when it is run
+	  under a hypervisor, potentially improving performance significantly
+	  over full virtualization.  However, when run without a hypervisor
+	  the kernel is theoretically slower and slightly larger.
+
+config PARAVIRT_TIME_ACCOUNTING
+	bool "Paravirtual steal time accounting"
+	depends on PARAVIRT
+	help
+	  Select this option to enable fine granularity task steal time
+	  accounting. Time spent executing other tasks in parallel with
+	  the current vCPU is discounted from the vCPU power. To account for
+	  that, there can be a small performance impact.
+
+	  If in doubt, say N here.
+
 endmenu
 
 config ARCH_SELECT_MEMORY_MODEL
@@ -680,6 +700,17 @@ source "drivers/cpufreq/Kconfig"
 source "kernel/power/Kconfig"
 source "drivers/acpi/Kconfig"
 
+config PARAVIRT_TIME_ACCOUNTING
+	bool "Paravirtual steal time accounting"
+	depends on PARAVIRT
+	help
+	  Select this option to enable fine granularity task steal time
+	  accounting. Time spent executing other tasks in parallel with
+	  the current vCPU is discounted from the vCPU power. To account for
+	  that, there can be a small performance impact.
+
+	  If in doubt, say N here.
+
 endmenu
 
 source "arch/loongarch/kvm/Kconfig"

arch/loongarch/configs/loongson3_defconfig

@@ -2204,3 +2204,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=60
 # CONFIG_STRICT_DEVMEM is not set
 # CONFIG_RUNTIME_TESTING_MENU is not set
 CONFIG_UNWINDER_ORC=y
+CONFIG_CMDLINE_EXTEND=y
+CONFIG_LOONGARCH_IOMMU=m
+CONFIG_CMDLINE="vfio_iommu_type1.allow_unsafe_interrupts=1 nokaslr"

arch/loongarch/include/asm/Kbuild

@@ -6,7 +6,6 @@ generic-y += mcs_spinlock.h
 generic-y += parport.h
 generic-y += early_ioremap.h
 generic-y += qrwlock.h
-generic-y += qspinlock.h
 generic-y += rwsem.h
 generic-y += segment.h
 generic-y += user.h

arch/loongarch/include/asm/device.h

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Arch specific extensions to struct device
+ *
+ * This file is released under the GPLv2
+ * Copyright (C) 2020 Loongson Technology Corporation Limited
+ */
+#ifndef _ASM_LOONGARCH_DEVICE_H
+#define _ASM_LOONGARCH_DEVICE_H
+
+struct dev_archdata {
+	/* hook for IOMMU specific extension */
+	void *iommu;
+	struct bus_dma_region *dma_range_map;
+	/*
+	 * On some old 7A chipset, dma address is different from physical
+	 * address, the main difference is that node id. For dma address
+	 * node id starts from bit 36, physical node id starts from
+	 * bit 44. The remaining address below node id is the same.
+	 */
+	unsigned long   dma_node_mask;
+	unsigned int	dma_node_off;
+};
+
+struct pdev_archdata {
+};
+
+struct dma_domain {
+	struct list_head node;
+	const struct dma_map_ops *dma_ops;
+	int domain_nr;
+};
+void add_dma_domain(struct dma_domain *domain);
+void del_dma_domain(struct dma_domain *domain);
+
+#endif /* _ASM_LOONGARCH_DEVICE_H*/

arch/loongarch/include/asm/kvm_csr.h

@@ -30,6 +30,7 @@
 		: [val] "+r" (__v)				\
 		: [reg] "i" (csr)				\
 		: "memory");					\
+	__v;							\
 })
 
 #define gcsr_xchg(v, m, csr)					\
@@ -181,6 +182,8 @@ __BUILD_GCSR_OP(tlbidx)
 #define kvm_save_hw_gcsr(csr, gid)	(csr->csrs[gid] = gcsr_read(gid))
 #define kvm_restore_hw_gcsr(csr, gid)	(gcsr_write(csr->csrs[gid], gid))
 
+#define kvm_read_clear_hw_gcsr(csr, gid)	(csr->csrs[gid] = gcsr_write(0, gid))
+
 int kvm_emu_iocsr(larch_inst inst, struct kvm_run *run, struct kvm_vcpu *vcpu);
 
 static __always_inline unsigned long kvm_read_sw_gcsr(struct loongarch_csrs *csr, int gid)
@@ -208,9 +211,7 @@ static __always_inline void kvm_change_sw_gcsr(struct loongarch_csrs *csr,
 	csr->csrs[gid] |= val & _mask;
 }
 
-#define KVM_PMU_PLV_ENABLE     (CSR_PERFCTRL_PLV0 |		\
-					CSR_PERFCTRL_PLV1 |	\
-					CSR_PERFCTRL_PLV2 |	\
-					CSR_PERFCTRL_PLV3)
+#define KVM_PMU_EVENT_ENABLED	(CSR_PERFCTRL_PLV0 | CSR_PERFCTRL_PLV1 | \
+					CSR_PERFCTRL_PLV2 | CSR_PERFCTRL_PLV3)
 
 #endif	/* __ASM_LOONGARCH_KVM_CSR_H__ */

arch/loongarch/include/asm/kvm_extioi.h

@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_EXTIOI_H
+#define LOONGARCH_EXTIOI_H
+
+#include <kvm/iodev.h>
+
+#define EXTIOI_IRQS			256
+#define EXTIOI_ROUTE_MAX_VCPUS		256
+#define EXTIOI_IRQS_U8_NUMS		(EXTIOI_IRQS / 8)
+#define EXTIOI_IRQS_U32_NUMS		(EXTIOI_IRQS_U8_NUMS / 4)
+#define EXTIOI_IRQS_U64_NUMS		(EXTIOI_IRQS_U32_NUMS / 2)
+/* map to ipnum per 32 irqs */
+#define EXTIOI_IRQS_NODETYPE_COUNT	16
+
+#define EXTIOI_BASE			0x1400
+#define EXTIOI_SIZE			0x900
+
+#define EXTIOI_NODETYPE_START		0xa0
+#define EXTIOI_NODETYPE_END		0xbf
+#define EXTIOI_IPMAP_START		0xc0
+#define EXTIOI_IPMAP_END		0xc7
+#define EXTIOI_ENABLE_START		0x200
+#define EXTIOI_ENABLE_END		0x21f
+#define EXTIOI_BOUNCE_START		0x280
+#define EXTIOI_BOUNCE_END		0x29f
+#define EXTIOI_ISR_START		0x300
+#define EXTIOI_ISR_END			0x31f
+#define EXTIOI_COREISR_START		0x400
+#define EXTIOI_COREISR_END		0x71f
+#define EXTIOI_COREMAP_START		0x800
+#define EXTIOI_COREMAP_END		0x8ff
+
+#define EIOINTC_VIRT_BASE		(0x40000000)
+#define EIOINTC_VIRT_SIZE		(0x1000)
+
+#define EIOINTC_VIRT_FEATURES		(0x0)
+#define EIOINTC_HAS_VIRT_EXTENSION	(0)
+#define EIOINTC_HAS_ENABLE_OPTION	(1)
+#define EIOINTC_HAS_INT_ENCODE		(2)
+#define EIOINTC_HAS_CPU_ENCODE		(3)
+#define EIOINTC_VIRT_HAS_FEATURES	((1U << EIOINTC_HAS_VIRT_EXTENSION) \
+					| (1U << EIOINTC_HAS_ENABLE_OPTION) \
+					| (1U << EIOINTC_HAS_INT_ENCODE)    \
+					| (1U << EIOINTC_HAS_CPU_ENCODE))
+#define EIOINTC_VIRT_CONFIG		(0x4)
+#define EIOINTC_ENABLE			(1)
+#define EIOINTC_ENABLE_INT_ENCODE	(2)
+#define EIOINTC_ENABLE_CPU_ENCODE	(3)
+
+#define LS3A_INTC_IP			8
+
+#define EXTIOI_SW_COREMAP_FLAG		(1 << 0)
+
+struct loongarch_extioi {
+	spinlock_t lock;
+	struct kvm *kvm;
+	struct kvm_io_device device;
+	struct kvm_io_device device_vext;
+	uint32_t num_cpu;
+	uint32_t features;
+	uint32_t status;
+
+	/* hardware state */
+	union nodetype {
+		u64 reg_u64[EXTIOI_IRQS_NODETYPE_COUNT / 4];
+		u32 reg_u32[EXTIOI_IRQS_NODETYPE_COUNT / 2];
+		uint16_t reg_u16[EXTIOI_IRQS_NODETYPE_COUNT];
+		u8 reg_u8[EXTIOI_IRQS_NODETYPE_COUNT * 2];
+	} nodetype;
+
+	/* one bit shows the state of one irq */
+	union bounce {
+		u64 reg_u64[EXTIOI_IRQS_U64_NUMS];
+		u32 reg_u32[EXTIOI_IRQS_U32_NUMS];
+		u8 reg_u8[EXTIOI_IRQS_U8_NUMS];
+	} bounce;
+
+	union isr {
+		u64 reg_u64[EXTIOI_IRQS_U64_NUMS];
+		u32 reg_u32[EXTIOI_IRQS_U32_NUMS];
+		u8 reg_u8[EXTIOI_IRQS_U8_NUMS];
+	} isr;
+	union coreisr {
+		u64 reg_u64[EXTIOI_ROUTE_MAX_VCPUS][EXTIOI_IRQS_U64_NUMS];
+		u32 reg_u32[EXTIOI_ROUTE_MAX_VCPUS][EXTIOI_IRQS_U32_NUMS];
+		u8 reg_u8[EXTIOI_ROUTE_MAX_VCPUS][EXTIOI_IRQS_U8_NUMS];
+	} coreisr;
+	union enable {
+		u64 reg_u64[EXTIOI_IRQS_U64_NUMS];
+		u32 reg_u32[EXTIOI_IRQS_U32_NUMS];
+		u8 reg_u8[EXTIOI_IRQS_U8_NUMS];
+	} enable;
+
+	/* use one byte to config ipmap for 32 irqs at once */
+	union ipmap {
+		u64 reg_u64;
+		u32 reg_u32[EXTIOI_IRQS_U32_NUMS / 4];
+		u8 reg_u8[EXTIOI_IRQS_U8_NUMS / 4];
+	} ipmap;
+	/* use one byte to config coremap for one irq */
+	union coremap {
+		u64 reg_u64[EXTIOI_IRQS / 8];
+		u32 reg_u32[EXTIOI_IRQS / 4];
+		u8 reg_u8[EXTIOI_IRQS];
+	} coremap;
+
+	DECLARE_BITMAP(sw_coreisr[EXTIOI_ROUTE_MAX_VCPUS][LS3A_INTC_IP], EXTIOI_IRQS);
+	uint8_t  sw_coremap[EXTIOI_IRQS];
+};
+
+void extioi_set_irq(struct loongarch_extioi *s, int irq, int level);
+int kvm_loongarch_register_extioi_device(void);
+int kvm_loongarch_reset_extioi(struct kvm *kvm);
+#endif /* LOONGARCH_EXTIOI_H */