Apply automatic changes to Manifest and README.rst

README.rst

@@ -23,6 +23,11 @@ Caravel Harness
 
 |License| |Documentation Status| |Build Status|
 
+**NOTE:**
+
+   Documentation for this project is being updated to reflect the changes
+   for the new redesigned version of Caravel.
+
 Table of contents
 =================
 
@@ -42,15 +47,9 @@ Overview
 Caravel is a template SoC for Efabless Open MPW and chipIgnite shuttles based on the Sky130 node from SkyWater Technologies. The
 current SoC architecture is given below.
 
-.. image:: docs/jpg/caravel_block_diagram.jpg
+.. image:: docs/source/_static/caravel_block_diagram.jpg
     :align: center
 
-.. raw:: html
-
-   <p align="center">
-   <img src="docs/source/_static/caravel_harness.png" width="50%" height="50%">
-   </p>
-
 Datasheet and detailed documentation exist `here <https://caravel-harness.readthedocs.io/>`__
 
 .. raw:: html
@@ -77,31 +76,61 @@ Datasheet and detailed documentation exist `here <https://caravel-harness.readth
 Caravel Architecture
 ====================
 
-Caravel is composed of three main sub-blocks: *management area*, *storage area*, and *user project area*.
+Caravel is composed of the harness frame plus two wrappers for drop-in modules for the *management area* and *user project area*.
+
+.. _harness-definition:
+
+Harness Definition
+------------------
+
+The harness itself contains the clocking module, DLL, user ID,
+housekeeping SPI, POR, and GPIO control.
+
+GPIO handling moved out of management SoC and into SPI.  SPI
+gets a wishbone interface;  the management SoC talks to the SPI
+through wishbone, not by taking over the 4-pin SPI interface.
+
+A new block like the ID has the mode at power-up for
+each GPIO.  Can be configured with a text file.  SPI pins are
+fixed for operation on startup.
+
+On power-up, the SPI automatically configures the
+GPIO.  Manual load is possible from both the SPI and from the
+wishbone bus.
+
+All functions within the harness but outside the management SoC
+are incorporated into one large module called "housekeeping".
+This includes a number of registers for all the included
+functions, with a "front door" SPI interface connected to the
+padframe through GPIO pins 1 to 4, and a "back door" wishbone
+interface connected to the management SoC.  The management Soc
+reserves the memory block at 0x26000000 for the
+housekeeping module.  The housekeeping module exchanges data
+with the management SoC via an interface that uses the byte-
+wide SPI register data.  A small state machine reads four
+contiguous wishbone addresses and an address decoder determines
+the corresponding SPI register.  The state machine stalls the
+SoC until all four bytes have been handled before returning the
+acknowledge signal.
 
 .. _management-area:
 
 Management Area
 --------------
 
-The managment area includes a  `picorv32 <https://github.com/cliffordwolf/picorv32>`__ based SoC that includes a number of periphrals like timers, uart, and gpio. The managemnt area runs firmware that can be used to:
+The management area is a drop-in module implemented as a separate repo.
+It typically includes a RISC-V based SoC that includes a number of peripherals like timers, uart, and gpio.
+The management area runs firmware that can be used to:
 
 -  Configure User Project I/O pads
 -  Observe and control User Project signals (through on-chip logic
    analyzer probes)
 -  Control the User Project power supply
 
-For a complete list of the SoC periphrals, check the  `memory map <https://github.com/efabless/caravel/blob/master/verilog/rtl/README>`__
-
-.. _storage-area:
-
-Storage Area
---------------
-
-The storage area is an auxiliary storage space for the managment SoC. It holds two dual port RAM blocks (1KB) generated by
-`OpenRAM <https://github.com/VLSIDA/OpenRAM.git>`__
+The management area implements SRAM for the management SoC.
 
-The storage area is only accessible by the management SoC.
+The default instantiation for the management core can be found `here <https://github.com/efabless/caravel_mgmt_soc_litex>`__ .
+See documentation of the management core for further details.
 
 .. _user-project-area:
 
@@ -121,8 +150,9 @@ Quick Start for User Projects
 =============================
 
 Your area is the full user space, so feel free to add your
-project there or create a differnt macro and harden it seperately then
-insert it into the ``user_project_wrapper`` for digital projects or insert it into ``user_project_analog_wrapper`` for analog projects.
+project there or create a different macro and harden it separately then
+insert it into the ``user_project_wrapper`` for digital projects or insert it
+into ``user_project_analog_wrapper`` for analog projects.
 
 .. _digital-user-project:
 
@@ -167,7 +197,7 @@ Analog user projects should adhere the following requirements:
 IMPORTANT
 ^^^^^^^^^
 
-Please make sure to run ``make compress`` before commiting anything to
+Please make sure to run ``make compress`` before committing anything to
 your repository. Avoid having 2 versions of the
 ``gds/user_project_wrapper.gds`` one compressed and the
 other not compressed.
@@ -226,6 +256,7 @@ MPW Two
 MPW One
 --------------
 
+-  `Caravel Legacy Repo (previous version used for MPW-ONE) <https://github.com/efabless/caravel_mpw-one>`__
 -  `Caravel User Project Features -- What are the utilities provided by caravel to the user project ? <https://youtu.be/zJhnmilXGPo>`__
 -  `Aboard Caravel -- How to integrate your design with Caravel? <https://youtu.be/9QV8SDelURk>`__
 -  `Things to Clarify About Caravel -- What versions to use with Caravel? <https://youtu.be/-LZ522mxXMw>`__