A machine code interpreter for RISC-V, in C++. This attempts at simulating the execution of a RISC-V machine code program. The program reads the machine code from a file, and executes it. The program is capable of executing the following instructions:
- Supports R-type instructions:
add,sub,and,or,xor,sll,srl,sra,slt,sltu - Supports I-type instructions:
addi,andi,ori,xori,slti,sltiu - Supports load and store instructions:
lb,lh,lw,lbu,lhu,sb,sh,sw - Supports branch instructions:
beq,bne,blt,bge,bltu,bgeu - Supports jump instructions:
jal,jalr - Supports upper immediate instructions:
lui,auipc - Single-stage core simulation
- Five-stage core simulation (WIP)
- C++ compiler (e.g., g++)
- Make (optional, for convenience)
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Clone the repository:
git clone https://github.com/fuzzymfx/yatch.git
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Compile the project:
g++ -std=c++20 -o .dist/yatch_simulator src/main.cpp
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Alternatively, you can use a Makefile (if provided):
make
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Prepare the memory files:
imem.txt: Contains the instruction memory.dmem.txt: Contains the data memory.
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Run the interpreter:
./.dist/yatch_simulator src/input
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Follow the prompts to provide the path to the memory files if not specified as a command-line argument.
imem.txt: Each line represents an 8-bit instruction memory value in binary format.dmem.txt: Each line represents an 8-bit data memory value in binary format.
- The state of the register file after each cycle is written to
RFResult.txt. - The state of the data memory after execution is written to
DmemSS_DMEMResult.txt.
00000000 00000000 00000000 10000011 00000000 01000000 00000001 00000011 00000000 00100000 10000001 10110011 00000000 00110000 00100100 00100011 11111111 11111111 11111111 11111111
01010101 01010101 01010101 01010101 00110011 00110011 00110011 00110011
This project is licensed under the MIT License. See the LICENSE file for details.
- RISC-V ISA Specification: The official RISC-V ISA manual.