This project involves the implementation of a custom CPU with specific features such as a multiplication/division unit, support for multi-cycle operations, and a caching mechanism.
- Introduced a specialized unit to handle multiplication and division operations.
- Enables the CPU to perform arithmetic computations more efficiently.
- Supports operations that require multiple clock cycles to complete.
- Improved timing and resource management for complex instructions.
- Added a caching mechanism to improve data access speed.
- Reduces the latency for fetching instructions and data from main memory.
The system architecture is depicted in the following diagram:
This diagram illustrates the integration of the multiplication/division unit, multi-cycle operation handling, and cache system within the CPU.
And the following table illustrates the input / output description of this system.
- Clone this repository:
git clone https://github.com/gary920209/CA_Finalproject.git