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Simple UART for FPGA v1.2
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@jakubcabal jakubcabal released this 23 Dec 20:46
· 13 commits to master since this release
v1.2
e556cb6
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Learn about vigilant mode.
  • Added double FF for safe CDC.
  • Fixed fake received transaction after FPGA boot without reset.
  • Added more precisely clock dividers, dividing with rounding.
  • UART loopback example is for CYC1000 board now.
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