typos, improve appendix

also c2000 doesn't guarantee exact adc early trigger cycles https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/612597/tms320f28379d-can-i-read-the-adc-result-just-in-time-in-cpu

xtightlycoupledio.adoc

@@ -1,7 +1,7 @@
 
 = XtightlyCoupledIO
 Jan Oleksiewicz <jnk0le@hotmail.com>
-:appversion: 3.2.46
+:appversion: 3.2.47
 :toc:
 :toclevels: 4
 :sectnums:
@@ -19,6 +19,7 @@ This document is released under a Creative Commons Attribution 4.0 International
 [cols="1,5",options=header]
 |====================================================================================
 | Version | Change
+| v3.2.47 | typos, improve appendix
 | v3.2.46 | fixed typos
 | v3.2.45 | typo, anti windup satration not considered
 | v3.2.44 | add code size comparisons to stm32f0 samples
@@ -3501,6 +3502,11 @@ specified in C <<typepunninginc>>
 
 from <<spraa85a>>, par 5.
 
+This is the kind of coding that appears very frequently, especially in c2000 codebases.
+Even though it is possible to coalesce all of that into a single write, compilers 
+can't do anything about that. Any optimization attempt by compilers will change
+the resulting side effects effectively breakig the code.
+
 [source, C]
 ----
 SysCtrlRegs.PCLKCR0.bit.rsvd1 = 0;
@@ -3734,7 +3740,7 @@ Therefore the explicit volatile load/store must always be porformed to safely us
 NOTE: interrupt overhead and related optimizations are out of scope of Xtighlycoupledio,
 therefore only a C function scenario is analysed. See <<xteic>> for further irq latency analysis.
 
-magic numbers and overall design according to <<an5305>>, that provides following assumptions:
+Magic numbers and overall design according to <<an5305>>, that provides following assumptions:
 
 - Vref (aka target voltage, not to be confused with ADC reference voltage) set by DAC on the
 differential ADC, or subtracted by ADC from result (`ADC_OFRy`).
@@ -3749,9 +3755,8 @@ only "normal" channels can generate `EOSMP` flag. Which is useless because
 this conversion can be interrupted by injected channels. (and injected channels 
 are used for control loops) The early trigger happens at least 36 cycles ahead 
 (@170MHz, 12,5 cycle conv, 60MHz adc clk) of the end of conversion, requiring additional wait loop.
-c2000 guarantees that early trigger covers only irq entry latency
 
-3p3z control loop irq, implemented using transposed direct form II IIR filter::
+3p3z compensator irq, implemented using transposed direct form II IIR filter::
 [source, C++]
 ----
 #include <algorithm>
@@ -3773,7 +3778,7 @@ typedef struct {
 
 	// keep those constants in memory as compilers are trying
 	// to put them right next to the code causing von neumann bottleneck
-	// It is possible to optimize those out when something fits 
+	// It is possible to optimize those out when something fits
 	// in `f.li` (Zfa) or `lui` (Zfinx) instructions, but that's a lot of manual work
 	float b[4];
 	float a[3]; // -1 indexed, as a0 is skipped
@@ -3843,6 +3848,8 @@ ADC1_IRQHandler():                   # @ADC1_IRQHandler()
 	ret
 ----
 
+NOTE: recent llvm versions allocate fa0-fa5 registers first
+
 armv7-m::
 [source, asm]
 ----