Verilog 8b10b encoder/decoder
clk
- input Clockrst
- input Reset (Active-HIGH)en
- input Enable (Active-HIGH)kin
- K- or D-symbol selection (1 - K
,0 - D
)din
- 8-bit data inputdout
- 10-bit data outputdisp
- Disparity flag outputkin_err
- K-symbol error output
clk
- input Clockrst
- input Reset (Active-HIGH)en
- input Enable (Active-HIGH)din
- 10-bit data inputdout
- 8-bit data outputkout
- K- or D-symbol flag (1 - K
,0 - D
)code_err
- Code error flag outputdisp
- Disparity outputdisp_err
- Disparity error flag output