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Merged mpfs_hal source code version 2.3.100.
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@mallynch
mallynch committed Feb 14, 2024
2 parents addd523 + f4ee3e0 commit e90c491
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Showing 19 changed files with 703 additions and 351 deletions.
2 changes: 1 addition & 1 deletion mpfs_hal/common/mss_axiswitch.c
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Original file line number Diff line number Diff line change
Expand Up @@ -168,7 +168,7 @@ int32_t MSS_AXISW_write_burstiness(mss_axisw_mport_t master_port_num,

if(burstiness_val == 0)
{
return -1;
return -1;
}
else
{
Expand Down
95 changes: 87 additions & 8 deletions mpfs_hal/common/mss_l2_cache.c
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ static const uint64_t g_init_marker = INIT_MARKER;
static void check_config_l2_scratchpad(void);

/***************************************************************************//**
* See hw_l2_scratch.h for details of how to use this function.
* See mss_l2_scratch.h for details of how to use this function.
*/
__attribute__((weak)) uint64_t end_l2_scratchpad_address(void)
{
Expand All @@ -39,7 +39,7 @@ __attribute__((weak)) uint64_t end_l2_scratchpad_address(void)
}

/***************************************************************************//**
* See hw_l2_scratch.h for details of how to use this function.
* See mss_l2_scratch.h for details of how to use this function.
*/
__attribute__((weak)) uint32_t num_cache_ways(void)
{
Expand All @@ -51,16 +51,36 @@ __attribute__((weak)) uint32_t num_cache_ways(void)
}

/***************************************************************************//**
* See hw_l2_scratch.h for details of how to use this function.
* See mss_l2_scratch.h for details of how to use this function.
*/
__attribute__((weak)) uint32_t my_num_cache_ways(void)
__attribute__((weak)) uint32_t my_num_dcache_ways(uint32_t hartid)
{
uint32_t num_ways = 0U;
uint32_t way_enable;
uint32_t bit_index;

//todo: return for my hart, assuming e51 here
way_enable = (uint32_t)LIBERO_SETTING_WAY_MASK_E51_DCACHE;
for (uint32_t current_way = 0; current_way <= LIBERO_SETTING_WAY_ENABLE; current_way++) {
/* disable evictions from all but current_way */
switch (hartid)
{
case 0:
way_enable = (uint32_t)LIBERO_SETTING_WAY_MASK_E51_DCACHE;
break;
case 1:
way_enable = (uint32_t)LIBERO_SETTING_WAY_MASK_U54_1_DCACHE;
break;
case 2:
way_enable = (uint32_t)LIBERO_SETTING_WAY_MASK_U54_2_DCACHE;
break;
case 3:
way_enable = (uint32_t)LIBERO_SETTING_WAY_MASK_U54_3_DCACHE;
break;
case 4:
way_enable = (uint32_t)LIBERO_SETTING_WAY_MASK_U54_4_DCACHE;
break;
}
}

bit_index = 0U;

while(bit_index < 16U)
Expand All @@ -75,7 +95,7 @@ __attribute__((weak)) uint32_t my_num_cache_ways(void)
}

/***************************************************************************//**
* See mss_uart.h for details of how to use this function.
* See mss_l2_scratch.h for details of how to use this function.
*/
__attribute__((weak)) void config_l2_cache(void)
{
Expand Down Expand Up @@ -197,7 +217,6 @@ __attribute__((weak)) void config_l2_cache(void)
mb();
}


/*==============================================================================
* Configure the L2 scratchpad based on linker symbols:
* __l2_scratchpad_vma_start
Expand Down Expand Up @@ -233,3 +252,63 @@ static void check_config_l2_scratchpad(void)

ASSERT(LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS >= n_scratchpad_ways);
}

/***************************************************************************//**
* See mss_l2_scratch.h for details of how to use this function.
*/
void flush_l2_cache(uint32_t hartid)
{
/*
* flush L2 Cache, way-by-way
* see https://forums.sifive.com/t/flush-invalidate-l1-l2-on-the-u54-mc/4483/9
* the thing to be wary of is the policy is random replacement by way,
* so there must be only 1 way enabled at a time...
* then, still need to go through ~2MiB (2MiB/16 per way) of reads to
* safely ensure the L2 is cleared...
*/

for (uint32_t current_way = 0; current_way <= LIBERO_SETTING_WAY_ENABLE; current_way++) {
/* disable evictions from all but current_way */
switch (hartid)
{
case 0:
__atomic_store_8(&CACHE_CTRL->WAY_MASK_E51_DCACHE, current_way, __ATOMIC_RELAXED);
break;
case 1:
__atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_1_DCACHE, current_way, __ATOMIC_RELAXED);
break;
case 2:
__atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_2_DCACHE, current_way, __ATOMIC_RELAXED);
break;
case 3:
__atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_3_DCACHE, current_way, __ATOMIC_RELAXED);
break;
case 4:
__atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_4_DCACHE, current_way, __ATOMIC_RELAXED);
break;
}

/* read 2MiB/16 from L2 zero device */
for (uint64_t i = 0u; i < 131u*1024u; i+=8u)
{ (void)*(volatile uint64_t *)(ZERO_DEVICE_BOTTOM + i); };
}
/* restore WayMask values... */
switch (hartid)
{
case 0:
__atomic_store_8(&CACHE_CTRL->WAY_MASK_E51_DCACHE, LIBERO_SETTING_WAY_MASK_E51_DCACHE, __ATOMIC_RELAXED);
break;
case 1:
__atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_1_DCACHE, LIBERO_SETTING_WAY_MASK_U54_1_DCACHE, __ATOMIC_RELAXED);
break;
case 2:
__atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_2_DCACHE, LIBERO_SETTING_WAY_MASK_U54_2_DCACHE, __ATOMIC_RELAXED);
break;
case 3:
__atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_3_DCACHE, LIBERO_SETTING_WAY_MASK_U54_3_DCACHE, __ATOMIC_RELAXED);
break;
case 4:
__atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_4_DCACHE, LIBERO_SETTING_WAY_MASK_U54_4_DCACHE, __ATOMIC_RELAXED);
break;
}
}
13 changes: 12 additions & 1 deletion mpfs_hal/common/mss_l2_cache.h
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Original file line number Diff line number Diff line change
Expand Up @@ -570,8 +570,19 @@ void config_l2_cache(void);
*/
uint8_t check_num_scratch_ways(uint64_t *start, uint64_t *end);

/***************************************************************************//**
Returns the number of cache ways
*/
uint32_t num_cache_ways(void);
uint32_t my_num_cache_ways(void);

uint32_t my_num_dcache_ways(uint32_t hartid);

/***************************************************************************//**
Flushes the L2 cache
*/
void flush_l2_cache(uint32_t hartid);

#ifdef __cplusplus
}
Expand Down
2 changes: 1 addition & 1 deletion mpfs_hal/common/mss_mpu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,7 @@ typedef struct
typedef struct
{
MPU_CFG PMPCFG[16U];
__IO MPU_FailStatus_TypeDef STATUS;
MPU_FailStatus_TypeDef STATUS;
} MPU_TypeDef;


Expand Down
13 changes: 13 additions & 0 deletions mpfs_hal/common/mss_peripherals.c
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Original file line number Diff line number Diff line change
Expand Up @@ -183,3 +183,16 @@ __attribute__((weak)) uint32_t mss_get_apb_bus_cr(void)
return (SYSREG->APBBUS_CR);
}

/***************************************************************************//**
* See mss_peripherals.h for details of how to use this function.
*/
__attribute__((weak)) void mss_turn_off_unused_ram_clks(void)
{
CAN0_RAM_OFF_IF_NOT_CONFIGURED();
CAN1_RAM_OFF_IF_NOT_CONFIGURED();
USB_RAM_OFF_IF_NOT_CONFIGURED();
MAC0_RAM_OFF_IF_NOT_CONFIGURED();
MAC1_RAM_OFF_IF_NOT_CONFIGURED();
MMC_RAM_OFF_IF_NOT_CONFIGURED();
DDR_RAM_OFF_IF_NOT_CONFIGURED();
}
37 changes: 36 additions & 1 deletion mpfs_hal/common/mss_peripherals.h
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Original file line number Diff line number Diff line change
Expand Up @@ -82,9 +82,33 @@ typedef enum mss_peripherals_ {
MSS_PERIPH_FIC0 = 32U,
MSS_PERIPH_FIC1 = 33U,
MSS_PERIPH_FIC2 = 34U,
MSS_PERIPH_FIC3 = 35U
MSS_PERIPH_FIC3 = 35U,
MSS_PERIPH_INVALID = 255U
} mss_peripherals;

#ifndef LIBERO_SETTING_TURN_OFF_RAM_IF_NOT_USED
#define LIBERO_SETTING_TURN_OFF_RAM_IF_NOT_USED
#endif

#ifndef LIBERO_SETTING_CONFIGURED_PERIPHERALS
#define LIBERO_SETTING_CONFIGURED_PERIPHERALS 0xFFFFFFFF
#endif

#define CAN0_RAM_OFF_IF_NOT_CONFIGURED() if((LIBERO_SETTING_CONFIGURED_PERIPHERALS\
& (1U<<15U))==0U) (SYSREG->RAM_SHUTDOWN_CR |= (1U <<0U))
#define CAN1_RAM_OFF_IF_NOT_CONFIGURED() if((LIBERO_SETTING_CONFIGURED_PERIPHERALS\
& (1U<<16U))==0U) (SYSREG->RAM_SHUTDOWN_CR |= (1U <<1U))
#define USB_RAM_OFF_IF_NOT_CONFIGURED() if((LIBERO_SETTING_CONFIGURED_PERIPHERALS\
& (1U<<2U))==0U) (SYSREG->RAM_SHUTDOWN_CR |= (1U <<2U))
#define MAC0_RAM_OFF_IF_NOT_CONFIGURED() if((LIBERO_SETTING_CONFIGURED_PERIPHERALS\
& (1U<<3U))==0U) (SYSREG->RAM_SHUTDOWN_CR |= (1U<<3U))
#define MAC1_RAM_OFF_IF_NOT_CONFIGURED() if((LIBERO_SETTING_CONFIGURED_PERIPHERALS\
& (1U<<4U))==0U) (SYSREG->RAM_SHUTDOWN_CR |= (1U<<4U))
#define MMC_RAM_OFF_IF_NOT_CONFIGURED() if((LIBERO_SETTING_CONFIGURED_PERIPHERALS\
& (3U<<0U))==0U) (SYSREG->RAM_SHUTDOWN_CR |= (1U<<5U))
#define DDR_RAM_OFF_IF_NOT_CONFIGURED() if((LIBERO_SETTING_DDRPHY_MODE &\
DDRPHY_MODE_MASK) == DDR_OFF_MODE)\
(SYSREG->RAM_SHUTDOWN_CR |= (1U<<7U))

/***************************************************************************//**
This function is used to turn on or off a peripheral. If contexts have been
Expand Down Expand Up @@ -162,6 +186,17 @@ void mss_set_apb_bus_cr(uint32_t reg_value);
*/
uint32_t mss_get_apb_bus_cr(void);

/***************************************************************************//**
This function is used to turn off RAM associated with peripherals that are
marked as unused in the MSS Configurator.
Example:
@code
mss_turn_off_unused_ram_clks();
@endcode
*/
void mss_turn_off_unused_ram_clks(void);


#ifdef __cplusplus
}
Expand Down
82 changes: 78 additions & 4 deletions mpfs_hal/common/nwc/mss_ddr.c
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Original file line number Diff line number Diff line change
Expand Up @@ -27,9 +27,11 @@
* Local Defines
*/
/* This string is updated if any change to ddr driver */
#define DDR_DRIVER_VERSION_STRING "0.4.023"
#define DDR_DRIVER_VERSION_STRING "0.4.024"
const char DDR_DRIVER_VERSION[] = DDR_DRIVER_VERSION_STRING;
/* Version | Comment */
/* 0.4.024 | Self-refresh is disabled from UI, api functions added for */
/* | turning self-refresh off and on. */
/* 0.4.023 | Changed default ADDCMD CLK push order for DDR4 to 0,45,90 */
/* 0.4.022 | Tidied comments and simulation reference- no code change */
/* 0.4.021 | Added options to increase post training tests during */
Expand Down Expand Up @@ -244,6 +246,57 @@ uint32_t noise_ena = 0x0;
* Public Functions - API
******************************************************************************/

void mpfs_hal_turn_ddr_selfrefresh_on(void)
{
uint32_t chip_selects;
/*
* Turn on user setting for self refresh
* Self-refresh control. Causes the controller to put the selected SDRAM
* rank(chip select) into self-refresh mode at the next refresh event. Each
* bit in init self refresh corresponds to the selected rank; asserting init
* self refresh[0] puts the devices connected to cs n[0] into self refresh,
* init self refresh[1] for cs n[1] and so on.
*/
if ((LIBERO_SETTING_DDRPHY_MODE & DDRPHY_MODE_RANK_MASK) ==
DDRPHY_MODE_TWO_RANKS)
{
chip_selects = 3U;
}
else
{
chip_selects = 1U;
}
DDRCFG->MC_BASE2.INIT_SELF_REFRESH.INIT_SELF_REFRESH = chip_selects;
}

void mpfs_hal_turn_ddr_selfrefresh_off(void)
{
/*
* Turn on user setting for self refresh
*/
DDRCFG->MC_BASE2.INIT_SELF_REFRESH.INIT_SELF_REFRESH = 0U;
}

uint32_t mpfs_hal_ddr_selfrefresh_status(void)
{
uint32_t status = 1U; /* self refresh on */

if ((LIBERO_SETTING_DDRPHY_MODE & DDRPHY_MODE_RANK_MASK) == DDRPHY_MODE_TWO_RANKS)
{
if( (DDRCFG->MC_BASE2.INIT_SELF_REFRESH_STATUS.INIT_SELF_REFRESH_STATUS & 3U) == 3U)
{
status = 0U;
}
}
else
{
if((DDRCFG->MC_BASE2.INIT_SELF_REFRESH_STATUS.INIT_SELF_REFRESH_STATUS & 1U) == 1U)
{
status = 0U;
}
}
return status;
}

/***************************************************************************//**
* ddr_state_machine(DDR_SS_COMMAND)
Expand Down Expand Up @@ -325,6 +378,26 @@ static uint32_t ddr_setup(void)

ddr_type = LIBERO_SETTING_DDRPHY_MODE & DDRPHY_MODE_MASK;

/*
* Usually in Renode we want to skip DDR training, as it is slow and does not
* do anything useful. If the user wants to explicitly simulate the training,
* then RENODE_SIM_DDR_TRAINING should be defined.
* The Training skip is achieved by reading from a register that should always
* return 0's in Hardware. In this case, the MPFS_DDRMock module will return
* a known pattern that will let us know we are in a simulation, and will skip
* the training.
* The RPC_RESET_MAIN_PLL register can usually only return 0x00 or 0x01, as
* the other bits are set to Rreturns0. This signature string "REND" will only
* ever be read when connected to the Renode MPFS_DDRMock module.
*/
#ifndef RENODE_SIM_DDR_TRAINING
if (0x52454E44 == CFG_DDR_SGMII_PHY->RPC_RESET_MAIN_PLL.RPC_RESET_MAIN_PLL)
{
ret_status |= DDR_SETUP_DONE;
ddr_training_state = DDR_TRAINING_FINISHED;
}
#endif

switch (ddr_training_state)
{
case DDR_TRAINING_INIT:
Expand Down Expand Up @@ -545,7 +618,7 @@ static uint32_t ddr_setup(void)

if (ddr_type == LPDDR4)
{
/* vrgen, modify during write leveling, turns off ODT */
/* vrgen, modify during write leveling, turns off ODT */
CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS =\
(dpc_bits & ~DDR_DPC_VRGEN_H_MASK)| (DPC_VRGEN_H_LPDDR4_WR_LVL_VAL << DDR_DPC_VRGEN_H_SHIFT);
CFG_DDR_SGMII_PHY->rpc3_ODT.rpc3_ODT = 0x0;
Expand Down Expand Up @@ -4056,8 +4129,7 @@ static void init_ddrc(void)
LIBERO_SETTING_CFG_CAL_READ_PERIOD;
DDRCFG->MC_BASE2.CFG_NUM_CAL_READS.CFG_NUM_CAL_READS =\
LIBERO_SETTING_CFG_NUM_CAL_READS;
DDRCFG->MC_BASE2.INIT_SELF_REFRESH.INIT_SELF_REFRESH =\
LIBERO_SETTING_INIT_SELF_REFRESH;
DDRCFG->MC_BASE2.INIT_SELF_REFRESH.INIT_SELF_REFRESH = 0U;
DDRCFG->MC_BASE2.INIT_POWER_DOWN.INIT_POWER_DOWN =\
LIBERO_SETTING_INIT_POWER_DOWN;
DDRCFG->MC_BASE2.INIT_FORCE_WRITE.INIT_FORCE_WRITE =\
Expand Down Expand Up @@ -4692,6 +4764,7 @@ MSS_DDR_user_commands
#endif

#ifdef DEBUG_DDR_INIT
#ifdef DEBUG_DDR_DDRCFG
void debug_read_ddrcfg(void)
{
(void)print_reg_array(g_debug_uart ,
Expand Down Expand Up @@ -4742,6 +4815,7 @@ void debug_read_ddrcfg(void)
return;
}
#endif
#endif


const uint8_t REFCLK_OFFSETS[][5U] = {
Expand Down
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