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fix timer
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ZR233 committed Jan 20, 2025
1 parent 2e5cc57 commit 8f4cfea
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Showing 8 changed files with 195 additions and 37 deletions.
22 changes: 11 additions & 11 deletions app/helloworld/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -21,17 +21,17 @@ fn main() {
// shutdown();
});

task::spawn_with_config(
|| {
info!("task2");
},
TaskConfig {
name: "task2".to_string(),
priority: 0,
stack_size: 0x1000 * 4,
},
)
.unwrap();
// task::spawn_with_config(
// || {
// info!("task2");
// },
// TaskConfig {
// name: "task2".to_string(),
// priority: 0,
// stack_size: 0x1000 * 4,
// },
// )
// .unwrap();

loop {
spin_delay(Duration::from_secs(1));
Expand Down
11 changes: 8 additions & 3 deletions crates/driver-interface/src/timer/mod.rs
Original file line number Diff line number Diff line change
@@ -1,4 +1,7 @@
use core::time::Duration;
use core::{
sync::atomic::{fence, Ordering},
time::Duration,
};

use crate::{interrupt_controller::IrqConfig, DriverGeneric};
use alloc::{boxed::Box, vec::Vec};
Expand Down Expand Up @@ -74,11 +77,13 @@ impl Timer {

fn add_event(&mut self, event: queue::Event) {
self.timer.set_irq_enable(false);
fence(Ordering::SeqCst);

let next_tick = self.q.add_and_next_tick(event);
let v = next_tick - self.timer.current_ticks();
self.timer.set_timeval(v);

self.timer.set_timeval(next_tick);

fence(Ordering::SeqCst);
self.timer.set_irq_enable(true);
}

Expand Down
9 changes: 7 additions & 2 deletions crates/sparreal-kernel/src/irq/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ use core::{cell::UnsafeCell, error::Error};

use alloc::{boxed::Box, collections::btree_map::BTreeMap, vec::Vec};
use driver_interface::interrupt_controller::*;
use log::{debug, error};
use log::{debug, error, warn};
use spin::Mutex;

use crate::{
Expand Down Expand Up @@ -147,7 +147,12 @@ impl Chip {
let irq = self.device.get_and_acknowledge_interrupt()?;

if let Some(handler) = unsafe { &mut *self.handlers.get() }.get(&irq) {
(handler)(irq);
let res = (handler)(irq);
if let IrqHandleResult::None = res {
return Some(());
}
} else {
warn!("IRQ {:?} no handler", irq);
}
self.device.end_interrupt(irq);
Some(())
Expand Down
8 changes: 8 additions & 0 deletions crates/sparreal-kernel/src/task/tcb.rs
Original file line number Diff line number Diff line change
Expand Up @@ -70,6 +70,14 @@ impl TaskControlBlock {
let task = Self(buffer.as_ptr());

unsafe {
let stack_top = task.stack().as_ptr().add(config.stack_size);

debug!(
"New task [{:?}], stack_top: {:p}",
task.info().name,
stack_top
);

PlatformImpl::cpu_context_init(
task.cpu_context_ptr(),
pc,
Expand Down
2 changes: 1 addition & 1 deletion crates/sparreal-rt/src/arch/aarch64/gic/gic_v2.rs
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ use super::*;

module_driver!(
name: "GICv2",
compatibles: &["arm,cortex-a15-gic"],
compatibles: &["arm,cortex-a15-gic", "arm,gic-400"],
probe: ProbeFnKind::InterruptController(probe_gic_v2),
);

Expand Down
1 change: 1 addition & 0 deletions crates/sparreal-rt/src/arch/aarch64/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -57,6 +57,7 @@ impl Platform for PlatformImpl {
unsafe fn cpu_context_init(ctx_ptr: *mut u8, pc: *const c_void, stack_top: *const u8) {
unsafe {
let ctx = &mut *(ctx_ptr as *mut trap::Context);
ctx.spsr = SPSR_EL1.get();
ctx.pc = pc as usize;
ctx.sp = stack_top as usize;
}
Expand Down
1 change: 1 addition & 0 deletions crates/sparreal-rt/src/arch/aarch64/timer.rs
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
use aarch64_cpu::registers::*;
use alloc::{boxed::Box, vec::Vec};
use log::debug;
use sparreal_kernel::driver_interface::{
DriverGeneric, ProbeFnKind, interrupt_controller::IrqConfig, timer::*,
};
Expand Down
178 changes: 158 additions & 20 deletions crates/sparreal-rt/src/arch/aarch64/trap.rs
Original file line number Diff line number Diff line change
Expand Up @@ -322,12 +322,9 @@ global_asm!(
serror_handler = sym handle_serror,
);

#[naked]
unsafe extern "C" fn context_switch(_current_task: &mut Context, _next_task: &Context) {
unsafe {
naked_asm!(
//x0
"
macro_rules! save_task_x {
() => {
"
add x0, x0, {size}
stp X29,X30, [x0,#-0x10]!
stp X27,X28, [x0,#-0x10]!
Expand All @@ -338,9 +335,13 @@ unsafe extern "C" fn context_switch(_current_task: &mut Context, _next_task: &Co
sub x0, x0, #0x90
mrs x9, SPSR_EL1
stp x9, x10, [x0,#-0x10]!
",
#[cfg(hard_float)]
"
"
};
}

macro_rules! save_task_q {
() => {
"
stp q30, q31, [x0,#-0x20]!
stp q28, q29, [x0,#-0x20]!
stp q26, q27, [x0,#-0x20]!
Expand All @@ -360,13 +361,22 @@ unsafe extern "C" fn context_switch(_current_task: &mut Context, _next_task: &Co
mrs x9, fpcr
mrs x10, fpsr
stp x9, x10, [x0,#-0x10]!
",
"
"
};
}

macro_rules! save_task_lr {
() => {
"
mov x9, sp
stp x9, lr, [x0,#-0x10]!
",
//x1
"
};
}

macro_rules! restore_task_x {
() => {
"
add x1, x1, {size}
ldp X29,X30, [x1,#-0x10]!
ldp X27,X28, [x1,#-0x10]!
Expand All @@ -377,9 +387,13 @@ unsafe extern "C" fn context_switch(_current_task: &mut Context, _next_task: &Co
sub x1, x1, #0x90
ldp x9, x10, [x1,#-0x10]!
msr SPSR_EL1, x9
",
#[cfg(hard_float)]
"
"
};
}

macro_rules! restore_task_q {
() => {
"
ldp q30, q31, [x1,#-0x20]!
ldp q28, q29, [x1,#-0x20]!
ldp q26, q27, [x1,#-0x20]!
Expand All @@ -399,12 +413,136 @@ unsafe extern "C" fn context_switch(_current_task: &mut Context, _next_task: &Co
ldp x9, x10, [x1,#-0x10]!
msr fpcr, x9
msr fpsr, x10
",
"
};
}

macro_rules! restore_task_lr {
() => {
"
ldp x9, lr, [x1,#-0x10]!
mov sp, x9
ret",
size = const size_of::<Context>()
)
ret"
};
}

#[cfg(hard_float)]
#[naked]
unsafe extern "C" fn context_switch(_current_task: &mut Context, _next_task: &Context) {
unsafe {
naked_asm!(
//x0
save_task_x!(),
save_task_q!(),
save_task_lr!(),
//x1
restore_task_x!(),
restore_task_q!(),
restore_task_lr!(),
size = const size_of::<Context>()
)
}
}

#[cfg(not(hard_float))]
#[naked]
unsafe extern "C" fn context_switch(_current_task: &mut Context, _next_task: &Context) {
unsafe {
naked_asm!(
//x0
save_task_x!(),
save_task_lr!(),
//x1
restore_task_x!(),
restore_task_lr!(),
size = const size_of::<Context>()
)
}
}

// #[naked]
// unsafe extern "C" fn context_switch(_current_task: &mut Context, _next_task: &Context) {
// unsafe {
// naked_asm!(
// //x0
// "
// add x0, x0, {size}
// stp X29,X30, [x0,#-0x10]!
// stp X27,X28, [x0,#-0x10]!
// stp X25,X26, [x0,#-0x10]!
// stp X23,X24, [x0,#-0x10]!
// stp X21,X22, [x0,#-0x10]!
// stp X19,X20, [x0,#-0x10]!
// sub x0, x0, #0x90
// mrs x9, SPSR_EL1
// stp x9, x10, [x0,#-0x10]!
// ",
// #[cfg(hard_float)]
// "
// stp q30, q31, [x0,#-0x20]!
// stp q28, q29, [x0,#-0x20]!
// stp q26, q27, [x0,#-0x20]!
// stp q24, q25, [x0,#-0x20]!
// stp q22, q23, [x0,#-0x20]!
// stp q20, q21, [x0,#-0x20]!
// stp q18, q19, [x0,#-0x20]!
// stp q16, q17, [x0,#-0x20]!
// stp q14, q15, [x0,#-0x20]!
// stp q12, q13, [x0,#-0x20]!
// stp q10, q11, [x0,#-0x20]!
// stp q8, q9, [x0,#-0x20]!
// stp q6, q7, [x0,#-0x20]!
// stp q4, q5, [x0,#-0x20]!
// stp q2, q3, [x0,#-0x20]!
// stp q0, q1, [x0,#-0x20]!
// mrs x9, fpcr
// mrs x10, fpsr
// stp x9, x10, [x0,#-0x10]!
// ",
// "
// mov x9, sp
// stp x9, lr, [x0,#-0x10]!
// ",
// //x1
// "
// add x1, x1, {size}
// ldp X29,X30, [x1,#-0x10]!
// ldp X27,X28, [x1,#-0x10]!
// ldp X25,X26, [x1,#-0x10]!
// ldp X23,X24, [x1,#-0x10]!
// ldp X21,X22, [x1,#-0x10]!
// ldp X19,X20, [x1,#-0x10]!
// sub x1, x1, #0x90
// ldp x9, x10, [x1,#-0x10]!
// msr SPSR_EL1, x9
// ",
// #[cfg(hard_float)]
// "
// ldp q30, q31, [x1,#-0x20]!
// ldp q28, q29, [x1,#-0x20]!
// ldp q26, q27, [x1,#-0x20]!
// ldp q24, q25, [x1,#-0x20]!
// ldp q22, q23, [x1,#-0x20]!
// ldp q20, q21, [x1,#-0x20]!
// ldp q18, q19, [x1,#-0x20]!
// ldp q16, q17, [x1,#-0x20]!
// ldp q14, q15, [x1,#-0x20]!
// ldp q12, q13, [x1,#-0x20]!
// ldp q10, q11, [x1,#-0x20]!
// ldp q8, q9, [x1,#-0x20]!
// ldp q6, q7, [x1,#-0x20]!
// ldp q4, q5, [x1,#-0x20]!
// ldp q2, q3, [x1,#-0x20]!
// ldp q0, q1, [x1,#-0x20]!
// ldp x9, x10, [x1,#-0x10]!
// msr fpcr, x9
// msr fpsr, x10
// ",
// "
// ldp x9, lr, [x1,#-0x10]!
// mov sp, x9
// ret",
// size = const size_of::<Context>()
// )
// }
// }

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