Hardware Design Automation for CNNs (Ongoing)

This project focusses on automatically converting the parameters of a pre-trained CNN model to a scalable hardware description controlled with parameters.

Current File Locations

Verilog Testbenches in Vivado_File/Simulation_Sources.

Verilog Design Files in Vivado_Files/Design_Sources.

Trained CNN with respective saved models and parameters in CNN_Files.