more cases for ushl

reilabs · Feb 9, 2025 · ab78024 · ab78024
1 parent fdadbbe
commit ab78024
Showing 1 changed file with 33 additions and 1 deletion.
diff --git a/compiler-rt/src/alu/ushl_sat/ushl_sat_i8.cairo b/compiler-rt/src/alu/ushl_sat/ushl_sat_i8.cairo
@@ -9,7 +9,16 @@ mod tests {
     use super::__llvm_ushl_sat_i8_i8;
     use crate::alu::test_case::TestCaseTwoArgs;
     #[cairofmt::skip]
-    pub const test_cases: [TestCaseTwoArgs; 35] = [
+    pub const test_cases: [TestCaseTwoArgs; 64] = [
+        TestCaseTwoArgs { lhs: 0b10000000, rhs: 0, expected: 0b10000000 },
+        TestCaseTwoArgs { lhs: 0b10000000, rhs: 1, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b10000000, rhs: 2, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b10000000, rhs: 3, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b10000000, rhs: 4, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b10000000, rhs: 5, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b10000000, rhs: 6, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b10000000, rhs: 7, expected: 0b11111111 },
+
         // All possible shifts of 255 from 0 throughout the whole input value length.
         // Since the MSB would be shifted out of the input type boundary, the output
         // clamps to the highest possible value.
@@ -22,6 +31,15 @@ mod tests {
         TestCaseTwoArgs { lhs: 0b11111111, rhs: 6, expected: 0b11111111 },
         TestCaseTwoArgs { lhs: 0b11111111, rhs: 7, expected: 0b11111111 },
 
+        TestCaseTwoArgs { lhs: 0b01111111, rhs: 0, expected: 0b01111111 },
+        TestCaseTwoArgs { lhs: 0b01111111, rhs: 1, expected: 0b11111110 },
+        TestCaseTwoArgs { lhs: 0b01111111, rhs: 2, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b01111111, rhs: 3, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b01111111, rhs: 4, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b01111111, rhs: 5, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b01111111, rhs: 6, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b01111111, rhs: 7, expected: 0b11111111 },
+
         // All possible shifts of 1 from 0 throughout the whole input value length.
         // Since the MSB would never be shifted out of the input type boundary,
         // it's just a regular bit shift left.
@@ -58,9 +76,23 @@ mod tests {
         TestCaseTwoArgs { lhs: 0b00000000, rhs: 7, expected: 0b00000000 },
 
         // Shifts of mixed 0/1 bit pattern
+        TestCaseTwoArgs { lhs: 0b10101010, rhs: 0, expected: 0b10101010 },
         TestCaseTwoArgs { lhs: 0b10101010, rhs: 1, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b10101010, rhs: 2, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b10101010, rhs: 3, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b10101010, rhs: 4, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b10101010, rhs: 5, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b10101010, rhs: 6, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b10101010, rhs: 7, expected: 0b11111111 },
+
+        TestCaseTwoArgs { lhs: 0b01010101, rhs: 0, expected: 0b01010101 },
         TestCaseTwoArgs { lhs: 0b01010101, rhs: 1, expected: 0b10101010 },
         TestCaseTwoArgs { lhs: 0b01010101, rhs: 2, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b01010101, rhs: 3, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b01010101, rhs: 4, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b01010101, rhs: 5, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b01010101, rhs: 6, expected: 0b11111111 },
+        TestCaseTwoArgs { lhs: 0b01010101, rhs: 7, expected: 0b11111111 },
     ];
 
     #[test]