Fix PR#68

Trivial edit, so made without PR. Signed-off-by: Robert Chyla (MIPS) <154632854+mipsrobert@users.noreply.github.com>
riscv-non-isa · Sep 16, 2024 · 7ee8127 · 7ee8127 · mipsrobert · Sep 16, 2024
1 parent 807fd24
commit 7ee8127
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/docs/RISC-V-N-Trace.adoc b/docs/RISC-V-N-Trace.adoc
@@ -1920,9 +1920,9 @@ void NTraceEncoderHandleRetired(uint64_t addr, uint32_t info)
         {
             // Update branch history buffer (add least significant bit)
             if (InfoIsBranchTaken(info))
-                encoHIST = (encoHIST << 1) | 0; // Mark branch as taken
+                encoHIST = (encoHIST << 1) | 1; // Mark branch as taken
             else
-                encoHIST = (encoHIST << 1) | 1; // Mark branch as not-taken
+                encoHIST = (encoHIST << 1) | 0; // Mark branch as not-taken
         }
         else
         {