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@shaurya0406 shaurya0406 released this 16 Aug 10:49
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RISCV_FSM
ab34dd3

RISC-V SoC FSM Implementation Release Notes

Version: 1.0.0
Release Date: Fri, Aug 16, 2024

Overview

This release introduces the FSM-based RISC-V System on Chip (SoC) implementation, encompassing a 5-stage processor architecture with integrated main memory for both instructions and data. The design is aimed at resource efficiency, flexibility, and ease of integration into various embedded systems.

Key Features

  1. 5-Stage Processor Architecture:

    • Fetch (FETCH): Captures instructions from the instruction memory based on the program counter (PC).
    • Decode (DECODE): Decodes the captured instruction to prepare for execution.
    • Execute (EXECUTE): Performs the actual instruction execution by operating on the ALU operands.
    • Memory Access (MEMORYACCESS): Interfaces with the data memory for load and store operations.
    • Writeback (WRITEBACK): Writes back the results of the execution to the destination registers.

  2. Main Memory Integration:

    • Unified main memory for both instruction and data storage, simplifying memory management and reducing hardware complexity.
    • Separate Interface for Instruction and Data Memory

  3. ALU Operation Support:

    • Supports various ALU operations required by RISC-V instruction types, including arithmetic, logic, and control instructions.

  4. Comprehensive Opcode Handling:

    • Decodes and handles various opcode types, including R-type, I-type, load, store, branch, JAL, JALR, LUI, AUIPC, system, and fence instructions.

  5. Initial Configuration:

    • Configurable PC reset value and memory depth, allowing customization based on specific application requirements.

  6. Stage Enable Signals:

    • Provides enable signals for ALU, memory access, writeback & CSR Stages, ensuring proper timing and control flow within the processor.

Enhancements

  • Resource Optimization: The use of a combined memory architecture significantly reduces the resource footprint, making the SoC ideal for embedded applications.
  • Ease of Integration: Modular design facilitates easy integration into existing systems and enhances maintainability.

Known Issues

  • Cache Implementation: This version does not include a cache memory system. Future releases may incorporate caching mechanisms to enhance performance.
  • Pipelining: The current implementation is unpipelined. Transitioning to a pipelined architecture is a potential improvement area.

Future Improvements

  • Development of a pipelined version of the FSM to improve instruction throughput.
  • Support for additional RISC-V extensions and custom instructions.
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