updated clock to 25.2 MHz for proper VGA signal 640x480@60

somhi · Jun 20, 2023 · f4dbfa6 · f4dbfa6
1 parent e43ff8b
commit f4dbfa6
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Showing 21 changed files with 64 additions and 1,048 deletions.
diff --git a/demistify/atlas_cyc/FlappyBird_atlas_cyc.qpf b/demistify/atlas_cyc/FlappyBird_atlas_cyc.qpf
@@ -18,12 +18,12 @@
 #
 # Quartus Prime
 # Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-# Date created = 20:26:28  June 19, 2023
+# Date created = 18:28:01  June 20, 2023
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "17.1"
-DATE = "20:26:28  June 19, 2023"
+DATE = "18:28:01  June 20, 2023"
 
 # Revisions
 

diff --git a/demistify/atlas_cyc/FlappyBird_atlas_cyc.qsf b/demistify/atlas_cyc/FlappyBird_atlas_cyc.qsf
@@ -18,7 +18,7 @@
 #
 # Quartus Prime
 # Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-# Date created = 20:26:28  June 19, 2023
+# Date created = 18:28:01  June 20, 2023
 #
 # -------------------------------------------------------------------------- #
 #
@@ -40,7 +40,7 @@ set_global_assignment -name FAMILY "Cyclone 10 LP"
 set_global_assignment -name DEVICE 10CL025YU256C8G
 set_global_assignment -name TOP_LEVEL_ENTITY atlas_top
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:26:28  JUNE 19, 2023"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:28:01  JUNE 20, 2023"
 set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
 set_global_assignment -name AUTO_MERGE_PLLS OFF
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

diff --git a/demistify/de10lite/FlappyBird_de10lite.qpf b/demistify/de10lite/FlappyBird_de10lite.qpf
@@ -18,12 +18,12 @@
 #
 # Quartus Prime
 # Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-# Date created = 20:08:45  June 19, 2023
+# Date created = 18:28:01  June 20, 2023
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "17.1"
-DATE = "20:08:45  June 19, 2023"
+DATE = "18:28:01  June 20, 2023"
 
 # Revisions
 

diff --git a/demistify/de10lite/FlappyBird_de10lite.qsf b/demistify/de10lite/FlappyBird_de10lite.qsf
@@ -18,7 +18,7 @@
 #
 # Quartus Prime
 # Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-# Date created = 20:08:45  June 19, 2023
+# Date created = 18:28:01  June 20, 2023
 #
 # -------------------------------------------------------------------------- #
 #

diff --git a/demistify/deca/deca_top.vhd b/demistify/deca/deca_top.vhd
@@ -385,13 +385,8 @@ begin
 			dac_LRCK  => i2s_Lr_o,
 			L_data    => std_logic_vector(dac_l),
 			R_data    => std_logic_vector(dac_r)
-		--	L_data    => std_logic_vector(dac_l_s),
-		--	R_data    => std_logic_vector(dac_r_s)
 		);
 
-	--dac_l_s <= ('0' & dac_l(14 downto 0));
-	--dac_r_s <= ('0' & dac_r(14 downto 0));
-
 	I2S_MCK <= i2s_Mck_o;
 	I2S_SCK <= i2s_Sck_o;
 	I2S_LR  <= i2s_Lr_o;

diff --git a/demistify/deca_mist/deca_mist_top.sv b/demistify/deca_mist/deca_mist_top.sv
@@ -1,46 +1,46 @@
 module deca_mist_top (
-    input  	 MAX10_CLK1_50,
+    input  	      MAX10_CLK1_50,
 
-    input [1:0]    KEY,
+    input [1:0]   KEY,
 
     // LED outputs
-    output [7:0]   LED,
+    output [7:0]  LED,
 
     // SDRAM interface
-    inout  [15:0]  DRAM_DQ, // SDRAM Data bus 16 Bits
-    output [12:0]  DRAM_ADDR, // SDRAM Address bus 13 Bits
-    output 	       DRAM_LDQM, // SDRAM Low-byte Data Mask
-    output 	       DRAM_UDQM, // SDRAM High-byte Data Mask
-    output 	       DRAM_WE_N, // SDRAM Write Enable
-    output 	       DRAM_CAS_N, // SDRAM Column Address Strobe
-    output         DRAM_RAS_N, // SDRAM Row Address Strobe
-    output 	       DRAM_CS_N, // SDRAM Chip Select
-    output [1:0]   DRAM_BA, // SDRAM Bank Address
-    output 	       DRAM_CLK, // SDRAM Clock
-    output 	       DRAM_CKE, // SDRAM Clock Enable
+    inout  [15:0] DRAM_DQ,       // SDRAM Data bus 16 Bits
+    output [12:0] DRAM_ADDR,     // SDRAM Address bus 13 Bits
+    output 	      DRAM_LDQM,     // SDRAM Low-byte Data Mask
+    output 	      DRAM_UDQM,     // SDRAM High-byte Data Mask
+    output 	      DRAM_WE_N,     // SDRAM Write Enable
+    output 	      DRAM_CAS_N,    // SDRAM Column Address Strobe
+    output        DRAM_RAS_N,    // SDRAM Row Address Strobe
+    output 	      DRAM_CS_N,     // SDRAM Chip Select
+    output [1:0]  DRAM_BA,       // SDRAM Bank Address
+    output 	      DRAM_CLK,      // SDRAM Clock
+    output 	      DRAM_CKE,      // SDRAM Clock Enable
 
     // SPI interface to arm io controller
-    inout 	 SPI_MISO_WSBD, //SPI_DO,
-    input 	 SPI_MOSI,      //SPI_DI,
-    input 	 SPI_SCLK_DABD, //SPI_SCK,
-    input 	 SPI_CS2,       //SPI_SS2,    (FPGA)
-    input 	 SPI_CS0_CLKBD, //SPI_SS3,    (OSD)
-    input 	 SPI_CS1,       //CONF_DATA0, (USER_IO)
-    input 	 SPI_SS4,       //SPI_SS4,    (SD DIRECT)
-//  input    RESET_N,       //RESET FROM SAM7S BUTTON
+    inout 	      SPI_MISO_WSBD, //SPI_DO,
+    input 	      SPI_MOSI,      //SPI_DI,
+    input 	      SPI_SCLK_DABD, //SPI_SCK,
+    input 	      SPI_CS2,       //SPI_SS2,    (FPGA)
+    input 	      SPI_CS0_CLKBD, //SPI_SS3,    (OSD)
+    input 	      SPI_CS1,       //CONF_DATA0, (USER_IO)
+    input 	      SPI_SS4,       //SPI_SS4,    (SD DIRECT)
+//  input         RESET_N,       //RESET FROM SAM7S BUTTON
 
     // Audio DAC DECA
-    output I2S_MCK,		//AUDIO_MCLK
-    output I2S_SCK,		//AUDIO_BCLK
-    output I2S_LR,		//AUDIO_WCLK
-    output I2S_D,		//AUDIO_DIN_MFP1
-    inout  AUDIO_GPIO_MFP5,
-    input  AUDIO_MISO_MFP4,
-    inout  AUDIO_RESET_n,
-    output AUDIO_SCLK_MFP3,
-    output AUDIO_SCL_SS_n,
-    inout  AUDIO_SDA_MOSI,
-    output AUDIO_SPI_SELECT,
+    output        I2S_MCK,		//AUDIO_MCLK
+    output        I2S_SCK,		//AUDIO_BCLK
+    output        I2S_LR,		  //AUDIO_WCLK
+    output        I2S_D,		  //AUDIO_DIN_MFP1
+    inout         AUDIO_GPIO_MFP5,
+    input         AUDIO_MISO_MFP4,
+    inout         AUDIO_RESET_n,
+    output        AUDIO_SCLK_MFP3,
+    output        AUDIO_SCL_SS_n,
+    inout         AUDIO_SDA_MOSI,
+    output        AUDIO_SPI_SELECT,
 
     //VIDEO
     output 	      VGA_HS,
@@ -95,13 +95,14 @@ module deca_mist_top (
 
   );
 
+  wire   RESET_DELAY_n;
+
   // VIDEO bits assignation
   assign VGA_R = r_aux[5:2];
   assign VGA_G = g_aux[5:2];
   assign VGA_B = b_aux[5:2];
 
   // AUDIO CODEC
-  wire   RESET_DELAY_n;
   assign RESET_DELAY_n = 1'b1;     // BUTTON;
 
   // Audio DAC DECA Output assignments

diff --git a/demistify/neptuno/FlappyBird_neptuno.qpf b/demistify/neptuno/FlappyBird_neptuno.qpf
@@ -18,12 +18,12 @@
 #
 # Quartus Prime
 # Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-# Date created = 20:05:27  June 19, 2023
+# Date created = 18:28:02  June 20, 2023
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "17.1"
-DATE = "20:05:27  June 19, 2023"
+DATE = "18:28:02  June 20, 2023"
 
 # Revisions
 

diff --git a/demistify/neptuno/FlappyBird_neptuno.qsf b/demistify/neptuno/FlappyBird_neptuno.qsf
@@ -18,7 +18,7 @@
 #
 # Quartus Prime
 # Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-# Date created = 20:05:27  June 19, 2023
+# Date created = 18:28:02  June 20, 2023
 #
 # -------------------------------------------------------------------------- #
 #
@@ -40,7 +40,7 @@ set_global_assignment -name FAMILY "Cyclone IV E"
 set_global_assignment -name DEVICE EP4CE55F23C8
 set_global_assignment -name TOP_LEVEL_ENTITY neptuno_top
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:05:27  JUNE 19, 2023"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:28:02  JUNE 20, 2023"
 set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
 set_global_assignment -name AUTO_MERGE_PLLS OFF
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

diff --git a/demistify/pll/50/pll_mist.v b/demistify/pll/50/pll_mist.v
@@ -90,9 +90,9 @@ module pll_mist (
 				.vcounderrange ());
 	defparam
 		altpll_component.bandwidth_type = "AUTO",
-		altpll_component.clk0_divide_by = 5,
+		altpll_component.clk0_divide_by = 2000,
 		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.clk0_multiply_by = 2,
+		altpll_component.clk0_multiply_by = 1007,
 		altpll_component.clk0_phase_shift = "0",
 		altpll_component.compensate_clock = "CLK0",
 		altpll_component.inclk0_input_frequency = 20000,
@@ -168,7 +168,7 @@ endmodule
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.174999"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -193,7 +193,7 @@ endmodule
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.17500000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -236,9 +236,9 @@ endmodule
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2000"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1007"
 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"

diff --git a/demistify/uareloaded/FlappyBird_uareloaded.qpf b/demistify/uareloaded/FlappyBird_uareloaded.qpf
@@ -18,12 +18,12 @@
 #
 # Quartus Prime
 # Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-# Date created = 20:22:25  June 19, 2023
+# Date created = 18:28:02  June 20, 2023
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "17.1"
-DATE = "20:22:25  June 19, 2023"
+DATE = "18:28:02  June 20, 2023"
 
 # Revisions
 

diff --git a/demistify/uareloaded/FlappyBird_uareloaded.qsf b/demistify/uareloaded/FlappyBird_uareloaded.qsf
@@ -18,7 +18,7 @@
 #
 # Quartus Prime
 # Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-# Date created = 20:22:25  June 19, 2023
+# Date created = 18:28:02  June 20, 2023
 #
 # -------------------------------------------------------------------------- #
 #

diff --git a/mist/deca_mist/FlappyBird.qpf b/mist/deca_mist/FlappyBird.qpf