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Generalize counter cell
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dopamane committed Jun 10, 2024
1 parent 4ebe676 commit 4738e42
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Showing 4 changed files with 41 additions and 36 deletions.
2 changes: 1 addition & 1 deletion lib/Bayeux/RgbCounter.hs
Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ newtype Rgb a = Rgb{ unRgb :: Writer [ModuleBody] a }

instance MonadRgb Rgb where
ctr = do
tell $ [ModuleBodyWire $ Wire [] $ WireStmt [WireOptionInput 1] "\\clk"] <> counter 32 "$my_counter" "\\unused"
tell $ [ModuleBodyWire $ Wire [] $ WireStmt [WireOptionInput 1] "\\clk"] <> counter 32 "\\$my_counter" "\\unused" "$my_counter" "$procStmt"
return $ SigSpecWireId "\\$my_counter"

at sigSpec ix = do
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65 changes: 35 additions & 30 deletions lib/Bayeux/Rtlil.hs
Original file line number Diff line number Diff line change
Expand Up @@ -258,41 +258,45 @@ initial outputIdent output =
in ConstantValue $ Value size bs

counter
:: Integer -- ^ width
-> Ident -- ^ old
-> Ident -- ^ new
:: Integer -- ^ width
-> WireId -- ^ old
-> WireId -- ^ new
-> CellId -- ^ add
-> ProcStmt -- ^ update
-> [ModuleBody]
counter w old new =
[ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth w] $ WireId $ "\\" <> old
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth w] $ WireId new
counter w old new addId procStmt =
[ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth w] old -- $ WireId $ "\\" <> old
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth w] new -- $ WireId new
, ModuleBodyCell $ addC
(CellId old)
addId
False
w
False
w
w
(SigSpecWireId $ WireId $ "\\" <> old)
(SigSpecWireId old)
(SigSpecConstant $ ConstantInteger 1)
(WireId new)
, ModuleBodyProcess $ Process
[]
"$procStmt"
(ProcessBody
[]
Nothing
[]
[Sync
(SyncStmt Posedge (SigSpecWireId "\\clk"))
[UpdateStmt
(DestSigSpec $ SigSpecWireId $ WireId $ "\\" <> old)
(SrcSigSpec $ SigSpecWireId $ WireId new)
]
]
)
ProcEndStmt
new
, ModuleBodyProcess $ updateP procStmt
(DestSigSpec $ SigSpecWireId old)
(SrcSigSpec $ SigSpecWireId new)
]

updateP :: ProcStmt -> DestSigSpec -> SrcSigSpec -> Process
updateP procStmt destSig srcSig = Process
[]
procStmt
(ProcessBody
[]
Nothing
[]
[Sync
(SyncStmt Posedge (SigSpecWireId "\\clk"))
[UpdateStmt destSig srcSig]
]
)
ProcEndStmt

data AttrStmt = AttrStmt Ident Constant
deriving (Eq, Read, Show)

Expand Down Expand Up @@ -555,13 +559,14 @@ modC = binaryCell . CellStmt "$mod"
divFloorC = binaryCell . CellStmt "$divfloor"
modFloorC = binaryCell . CellStmt "$modfloor"

-- | Y = S ? B : A
muxC
:: CellId
-> Integer -- ^ \WIDTH
-> SigSpec -- ^ \A
-> SigSpec -- ^ \B
-> SigSpec -- ^ \S
-> WireId
-> Integer -- ^ WIDTH
-> SigSpec -- ^ A
-> SigSpec -- ^ B
-> SigSpec -- ^ S
-> WireId -- ^ Y
-> Cell
muxC cellId w a b s y = Cell
[]
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2 changes: 1 addition & 1 deletion test/Test/Bayeux/Rtlil.hs
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ tests =
(SigSpecWireId "\\pwm_b")
, prettyTest "fiatLux" fiatLux
, prettyTest "add" $ addC "\\adder" False 32 False 32 33 (SigSpecWireId "\\a") (SigSpecWireId "\\b") "\\y"
, prettyTest "counter" $ counter 8 "\\old" "\\new"
, prettyTest "counter" $ counter 8 "\\old" "\\new" "$old" "$procStmt"
]
, testGroup "synth"
[ synthTest "led" rtlilLed
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8 changes: 4 additions & 4 deletions test/Test/Bayeux/Rtlil/golden/counter.pretty
Original file line number Diff line number Diff line change
@@ -1,13 +1,13 @@
[ wire width 8 \\old
[ wire width 8 \old
, wire width 8 \new
,
cell $add \old
cell $add $old
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
connect \A \\old
connect \A \old
connect \B 1
connect \Y \new
end
Expand All @@ -18,6 +18,6 @@ process $procStmt


sync posedge \clk
update \\old \new
update \old \new
end
]

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