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{-# LANGUAGE GeneralizedNewtypeDeriving #-} | ||
{-# LANGUAGE OverloadedStrings #-} | ||
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module Bayeux.RgbCounter | ||
( prog | ||
, compile | ||
, cycleProg | ||
, cycleCompile | ||
) where | ||
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import Bayeux.Rtlil | ||
import Control.Monad.State | ||
import Control.Monad.Writer | ||
import Data.String | ||
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class Monad m => MonadRgb m where | ||
ctr :: m SigSpec | ||
at :: SigSpec -> Integer -> m SigSpec | ||
rgb :: SigSpec -> SigSpec -> SigSpec -> m () | ||
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prog :: MonadRgb m => m () | ||
prog = do | ||
c <- ctr | ||
r <- c `at` 24 | ||
g <- c `at` 23 | ||
b <- c `at` 22 | ||
rgb r g b | ||
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newtype Rgb a = Rgb{ unRgb :: Writer [ModuleBody] a } | ||
deriving (Functor, Applicative, Monad, MonadWriter [ModuleBody]) | ||
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instance MonadRgb Rgb where | ||
ctr = do | ||
tell $ [ModuleBodyWire $ Wire [] $ WireStmt [WireOptionInput 1] "\\clk"] <> counter 32 "\\$my_counter" "\\unused" "$my_counter" "$procStmt" | ||
return $ SigSpecWireId "\\$my_counter" | ||
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at sigSpec ix = do | ||
tell | ||
[ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth 1] n | ||
, ModuleBodyConnStmt $ ConnStmt (SigSpecWireId n) (SigSpecSlice sigSpec ix Nothing) | ||
] | ||
return $ SigSpecWireId n | ||
where | ||
n | ix == 24 = "\\pwm_r" | ||
| ix == 23 = "\\pwm_g" | ||
| otherwise = "\\pwm_b" | ||
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rgb r g b = do | ||
tell [ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionOutput 2] "\\red" | ||
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionOutput 3] "\\green" | ||
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionOutput 4] "\\blue" | ||
, ModuleBodyCell $ sbRgbaDrv r g b | ||
] | ||
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compile :: Rgb a -> File | ||
compile = top . execWriter . unRgb | ||
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class MonadProcess m where | ||
process :: (SigSpec -> m SigSpec) -> m SigSpec | ||
increment :: SigSpec -> m SigSpec | ||
eq :: SigSpec -> SigSpec -> m SigSpec | ||
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-- | If S == 1 then B else A | ||
mux :: SigSpec -- ^ S | ||
-> SigSpec -- ^ A | ||
-> SigSpec -- ^ B | ||
-> m SigSpec -- ^ Y | ||
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cycleProg :: MonadProcess m => MonadRgb m => m () | ||
cycleProg = do | ||
t <- process $ \timer -> do | ||
t1Sec <- timer `eq` second | ||
timer' <- increment timer | ||
mux t1Sec timer' zero | ||
tEqZ <- t `eq` zero | ||
c <- process $ \color -> do | ||
cEqBlue <- color `eq` two | ||
c' <- increment color | ||
color' <- mux cEqBlue c' zero | ||
mux tEqZ color color' | ||
pwmR <- c `eq` zero | ||
pwmG <- c `eq` one | ||
pwmB <- c `eq` two | ||
rgb pwmR pwmG pwmB | ||
where | ||
constSig = SigSpecConstant . ConstantInteger | ||
zero = constSig 0 | ||
one = constSig 1 | ||
two = constSig 2 | ||
second = constSig 12000000 | ||
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newtype Rtl a = Rtl{ unRtl :: WriterT [ModuleBody] (State Integer) a } | ||
deriving ( Functor, Applicative, Monad | ||
, MonadWriter [ModuleBody] | ||
, MonadState Integer | ||
) | ||
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instance MonadRgb Rtl where | ||
ctr = do | ||
tell $ [ModuleBodyWire $ Wire [] $ WireStmt [WireOptionInput 1] "\\clk"] <> counter 32 "\\$my_counter" "\\unused" "$my_counter" "$procStmt" | ||
return $ SigSpecWireId "\\$my_counter" | ||
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at sigSpec ix = do | ||
tell | ||
[ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth 1] n | ||
, ModuleBodyConnStmt $ ConnStmt (SigSpecWireId n) (SigSpecSlice sigSpec ix Nothing) | ||
] | ||
return $ SigSpecWireId n | ||
where | ||
n | ix == 24 = "\\pwm_r" | ||
| ix == 23 = "\\pwm_g" | ||
| otherwise = "\\pwm_b" | ||
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rgb r g b = do | ||
tell [ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionOutput 2] "\\red" | ||
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionOutput 3] "\\green" | ||
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionOutput 4] "\\blue" | ||
, ModuleBodyCell $ sbRgbaDrv r g b | ||
] | ||
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instance MonadProcess Rtl where | ||
process f = do | ||
i <- get | ||
modify (+ 1) | ||
let old = fromString $ "\\ident" <> show i | ||
j <- get | ||
modify (+ 1) | ||
let procStmt = fromString $ "$ident" <> show j | ||
tell [ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth 32] old] | ||
srcSig <- f $ SigSpecWireId old | ||
tell [ModuleBodyProcess $ updateP procStmt | ||
(DestSigSpec $ SigSpecWireId old) | ||
(SrcSigSpec $ srcSig) | ||
] | ||
return $ SigSpecWireId old | ||
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increment a = do | ||
i <- get | ||
modify (+ 1) | ||
let y = fromString $ "\\ident" <> show i | ||
j <- get | ||
modify (+ 1) | ||
let cId = fromString $ "$ident" <> show j | ||
tell [ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth 32] y | ||
, ModuleBodyCell $ addC cId False 32 False 32 32 a (SigSpecConstant $ ConstantInteger 1) y | ||
] | ||
return $ SigSpecWireId y | ||
eq a b = do | ||
i <- get | ||
modify (+ 1) | ||
let y = fromString $ "\\ident" <> show i | ||
j <- get | ||
modify (+ 1) | ||
let cId = fromString $ "$ident" <> show j | ||
tell [ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth 1] y | ||
, ModuleBodyCell $ eqC cId False 32 False 32 1 a b y | ||
] | ||
return $ SigSpecWireId y | ||
mux s a b = do | ||
i <- get | ||
modify (+ 1) | ||
let y = fromString $ "\\ident" <> show i | ||
j <- get | ||
modify (+ 1) | ||
let cId = fromString $ "$ident" <> show j | ||
tell [ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth 32] y | ||
, ModuleBodyCell $ muxC cId 32 a b s y | ||
] | ||
return $ SigSpecWireId y | ||
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cycleCompile :: Rtl a -> File | ||
cycleCompile = top . clocked . flip evalState 1 . execWriterT . unRtl | ||
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clocked :: [ModuleBody] -> [ModuleBody] | ||
clocked = (ModuleBodyWire (Wire [] $ WireStmt [WireOptionInput 1] "\\clk") :) |
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