Fixup tests to use rtlil cells

standardsemiconductor · Jun 9, 2024 · cf1c618 · cf1c618
1 parent f6e9382
commit cf1c618
Showing 1 changed file with 13 additions and 52 deletions.
diff --git a/test/Test/Bayeux/Rtlil.hs b/test/Test/Bayeux/Rtlil.hs
@@ -61,58 +61,19 @@ rtlilLed = File Nothing
       , ModuleBodyWire $ Wire [] $ WireStmt [WireOptionOutput 4] "\\LED_B"
       , ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth 26] "\\counter"
       , ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth 32] "\\counter_plus_one"
-      , ModuleBodyCell $ Cell
-          []
-          (CellStmt "$add" "$increment")
-          [ CellParameter Nothing "\\A_SIGNED" $ ConstantInteger 0
-          , CellParameter Nothing "\\A_WIDTH"  $ ConstantInteger 26
-          , CellParameter Nothing "\\B_SIGNED" $ ConstantInteger 0
-          , CellParameter Nothing "\\B_WIDTH"  $ ConstantInteger 32
-          , CellParameter Nothing "\\Y_WIDTH"  $ ConstantInteger 32
-          , CellConnect "\\A" $ SigSpecWireId "\\counter"
-          , CellConnect "\\B" $ SigSpecConstant $ ConstantInteger 1
-          , CellConnect "\\Y" $ SigSpecWireId "\\counter_plus_one"
-          ]
-          CellEndStmt
-      , ModuleBodyCell $ Cell
-          []
-          (CellStmt "$not" "$not$1")
-          [ CellParameter Nothing "\\A_SIGNED" $ ConstantInteger 0
-          , CellParameter Nothing "\\A_WIDTH"  $ ConstantInteger 1
-          , CellParameter Nothing "\\Y_WIDTH"  $ ConstantInteger 1
-          , CellConnect "\\A" $ SigSpecSlice
-              (SigSpecWireId "\\counter")
-              23
-              Nothing
-          , CellConnect "\\Y" $ SigSpecWireId "\\LED_R"
-          ]
-          CellEndStmt
-      , ModuleBodyCell $ Cell
-          []
-          (CellStmt "$not" "$not$2")
-          [ CellParameter Nothing "\\A_SIGNED" $ ConstantInteger 0
-          , CellParameter Nothing "\\A_WIDTH"  $ ConstantInteger 1
-          , CellParameter Nothing "\\Y_WIDTH"  $ ConstantInteger 1
-          , CellConnect "\\A" $ SigSpecSlice
-              (SigSpecWireId "\\counter")
-              24
-              Nothing
-          , CellConnect "\\Y" $ SigSpecWireId "\\LED_G"
-          ]
-          CellEndStmt
-      , ModuleBodyCell $ Cell
-          []
-          (CellStmt "$not" "$not$3")
-          [ CellParameter Nothing "\\A_SIGNED" $ ConstantInteger 0
-          , CellParameter Nothing "\\A_WIDTH"  $ ConstantInteger 1
-          , CellParameter Nothing "\\Y_WIDTH"  $ ConstantInteger 1
-          , CellConnect "\\A" $ SigSpecSlice
-              (SigSpecWireId "\\counter")
-              25
-              Nothing
-          , CellConnect "\\Y" $ SigSpecWireId "\\LED_B"
-          ]
-          CellEndStmt
+      , ModuleBodyCell $ addC "$increment" False 26 False 32 32
+          (SigSpecWireId "\\counter")
+          (SigSpecConstant $ ConstantInteger 1)
+          "\\counter_plus_one"
+      , ModuleBodyCell $ notC "$not$1" False 1 1
+          (SigSpecSlice (SigSpecWireId "\\counter") 23 Nothing)
+          "\\LED_R"
+      , ModuleBodyCell $ notC "$not$2" False 1 1
+          (SigSpecSlice (SigSpecWireId "\\counter") 24 Nothing)
+          "\\LED_G"
+      , ModuleBodyCell $ notC "$not$3" False 1 1
+          (SigSpecSlice (SigSpecWireId "\\counter") 25 Nothing)
+          "\\LED_B"
       , ModuleBodyProcess $ Process
           []
           "$run"