Add SB_RGBA_DRV cell, fix constant string pretty printer

standardsemiconductor · Jun 4, 2024 · f4fe638 · f4fe638
1 parent 432de03
commit f4fe638
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Showing 3 changed files with 40 additions and 1 deletion.
diff --git a/src/Bayeux/Rtlil.hs b/src/Bayeux/Rtlil.hs
@@ -41,6 +41,7 @@ module Bayeux.Rtlil
   , CellType(..)
   , CellBodyStmt(..)
   , CellEndStmt(..)
+  , sbRgbaDrv
   , -- ** Processes
     Process(..)
   , ProcStmt(..)
@@ -159,7 +160,7 @@ instance Pretty Constant where
   pretty = \case
     ConstantValue   v -> pretty v
     ConstantInteger i -> pretty i
-    ConstantString  t -> pretty t
+    ConstantString  t -> dquotes $ pretty t
 
 data ModuleEndStmt = ModuleEndStmt
   deriving (Eq, Read, Show)
@@ -294,6 +295,25 @@ data CellEndStmt = CellEndStmt
 instance Pretty CellEndStmt where
   pretty _ = "end" <> hardline
 
+sbRgbaDrv :: Cell
+sbRgbaDrv = Cell
+  [AttrStmt (Ident "\\module_not_derived") $ ConstantInteger 1]
+  (CellStmt (CellType $ Ident "\\SB_RGBA_DRV") (CellId $ Ident "\\RGBA_DRIVER"))
+  [ CellParameter Nothing (Ident "\\CURRENT_MODE") $ ConstantString "0b1"
+  , CellParameter Nothing (Ident "\\RGB0_CURRENT") $ ConstantString "0b111111"
+  , CellParameter Nothing (Ident "\\RGB1_CURRENT") $ ConstantString "0b111111"
+  , CellParameter Nothing (Ident "\\RGB2_CURRENT") $ ConstantString "0b111111"
+  , CellConnect (Ident "\\CURREN") $ SigSpecConstant $ ConstantValue $ Value 1 [B1]
+  , CellConnect (Ident "\\RGB0") $ SigSpecWireId $ WireId $ Ident "\\red"
+  , CellConnect (Ident "\\RGB0PWM") $ SigSpecWireId $ WireId $ Ident "\\pwm_r"
+  , CellConnect (Ident "\\RGB1") $ SigSpecWireId $ WireId $ Ident "\\green"
+  , CellConnect (Ident "\\RGB1PWM") $ SigSpecWireId $ WireId $ Ident "\\pwm_g"
+  , CellConnect (Ident "\\RGB2") $ SigSpecWireId $ WireId $ Ident "\\blue"
+  , CellConnect (Ident "\\RGB2PWM") $ SigSpecWireId $ WireId $ Ident "\\pwm_b"
+  , CellConnect (Ident "\\RGBLEDEN") $ SigSpecConstant $ ConstantValue $ Value 1 [B1]
+  ]
+  CellEndStmt
+
 data Process = Process [AttrStmt] ProcStmt ProcessBody ProcEndStmt
   deriving (Eq, Read, Show)
 

diff --git a/test/Test/Bayeux/Rtlil.hs b/test/Test/Bayeux/Rtlil.hs
@@ -27,6 +27,8 @@ tests =
       TIO.writeFile f $ render $ pretty rtlilLed
       let c = "yosys -q -p \"synth_ice40\" -f rtlil " <> f
       (ExitSuccess @=?) =<< waitForProcess =<< spawnCommand c
+  , goldenVsString "pretty-sbRgbaDrv" (curDir </> "pretty-sbRgbaDrv" <.> "golden") $ return $
+      fromString $ T.unpack $ render $ pretty sbRgbaDrv
   ]
 
 curDir :: FilePath

diff --git a/test/Test/Bayeux/Rtlil/pretty-sbRgbaDrv.golden b/test/Test/Bayeux/Rtlil/pretty-sbRgbaDrv.golden
@@ -0,0 +1,17 @@
+attribute \module_not_derived 1
+cell \SB_RGBA_DRV \RGBA_DRIVER
+
+  parameter \CURRENT_MODE "0b1"
+  parameter \RGB0_CURRENT "0b111111"
+  parameter \RGB1_CURRENT "0b111111"
+  parameter \RGB2_CURRENT "0b111111"
+  connect \CURREN 1'1
+  connect \RGB0 \red
+  connect \RGB0PWM \pwm_r
+  connect \RGB1 \green
+  connect \RGB1PWM \pwm_g
+  connect \RGB2 \blue
+  connect \RGB2PWM \pwm_b
+  connect \RGBLEDEN 1'1
+
+end