Skip to content

Commit

Permalink
remove useless comments
Browse files Browse the repository at this point in the history
  • Loading branch information
ken4647 committed Jan 14, 2025
1 parent 4b5e851 commit dbefecc
Show file tree
Hide file tree
Showing 2 changed files with 0 additions and 2 deletions.
1 change: 0 additions & 1 deletion api/ruxos_posix_api/src/imp/pipe.rs
Original file line number Diff line number Diff line change
Expand Up @@ -117,7 +117,6 @@ impl Pipe {

pub fn write_end_close(&self) -> bool {
let write_end_count = Arc::weak_count(&self.buffer);
// error!("Pipe::write_end_close <= buffer: {:#?} {:#?}", write_end_count, Arc::as_ptr(&self.buffer));
write_end_count == 0
}
}
Expand Down
1 change: 0 additions & 1 deletion modules/ruxhal/src/arch/x86_64/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -174,7 +174,6 @@ pub fn flush_tlb(vaddr: Option<VirtAddr>) {
#[inline]
#[cfg(all(feature = "irq", feature = "paging", feature = "smp"))]
pub(crate) fn flush_tlb_ipi_handler() {
// error!("flush TLB entry in IPI handler");
let guard = kernel_guard::NoPreempt::new();
unsafe {
let mut flushing_addresses = FLUSHING_ADDRESSES[this_cpu_id()].lock();
Expand Down

0 comments on commit dbefecc

Please sign in to comment.