calint / zen-x Star 1 Code Issues Pull requests experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent cpu fpga verilog xilinx vivado 16-bit vintage cmod-s7 Updated May 29, 2024 Verilog
calint / riscv Star 1 Code Issues Pull requests experiments implementing a risc-v cpu to gain experience with verilog and minimalistic cpu design cpu fpga verilog vivado risc-v iverilog riscv32i cmod-s7 Updated Dec 21, 2024 Verilog
calint / znxcr Star 0 Code Issues Pull requests experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent cpu fpga verilog 16-bit cmod-s7 Updated May 29, 2024 Verilog
calint / zen-one Star 0 Code Issues Pull requests experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga cmod s7 from digilent cpu fpga verilog vivado 16-bit iverilog vintage cmod-s7 Updated May 29, 2024 Verilog