Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis
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Dec 9, 2022 - AGS Script
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memory-design
Here are 6 public repositories matching this topic...
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Sep 3, 2022 - C#
This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.
fpga ram hardware verilog synchronous testbench digital-circuits hardware-description-language single-port fpga-programming memory-design
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Aug 24, 2024 - Verilog
Behavioral architecture of a read/write cycle controller for a DRAM chip.
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May 26, 2023 - VHDL
PESU Sem 3: Mini project for Digital Design and Computer Organization
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Nov 17, 2024 - Verilog
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