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Somewhat related to D105338. While it is up for discussion whether or not volatile store traps, so far there has been no complaints that volatile load/cmpxchg/atomicrmw also may trap. And even if simplifycfg currently concervatively believes that to be the case, instcombine does not: https://godbolt.org/z/5vhv4K5b8 Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D105343
For now only expose a builder for the LLVM pointer type. Reviewed By: jpienaar, ftynse Differential Revision: https://reviews.llvm.org/D105346
This tries to bail out if the PHI is in a `catchswitch` BB in InstCombine. A PHI cannot be combined into a non-PHI instruction if it is in a `catchswitch` BB, because `catchswitch` BB cannot have any non-PHI instruction other than `catchswitch` itself. The given test case started crashing after D98058. Reviewed By: lebedev.ri, rnk Differential Revision: https://reviews.llvm.org/D105309
…resent the result of unreachable instrs Mimics similar change for InstCombine: ce192ce / D104602 All these uses are in blocks that aren't reachable from function's entry, and said blocks are removed by SimplifyCFG itself, so we can't really test this change.
… addressing mode usage. We're trying to match a few pointer computation patterns here for re-association opportunities. 1) Isolating a constant operand to be on the RHS, e.g.: G_PTR_ADD(BASE, G_ADD(X, C)) -> G_PTR_ADD(G_PTR_ADD(BASE, X), C) 2) Folding two constants in each sub-tree as long as such folding doesn't break a legal addressing mode. G_PTR_ADD(G_PTR_ADD(BASE, C1), C2) -> G_PTR_ADD(BASE, C1+C2) AArch64 code size improvements on CTMark with -Os: Program before after diff pairlocalalign 251048 251044 -0.0% consumer-typeset 421820 421812 -0.0% kc 431348 431320 -0.0% SPASS 413404 413300 -0.0% clamscan 384396 384220 -0.0% tramp3d-v4 370640 370412 -0.1% lencod 432096 431772 -0.1% bullet 479400 478796 -0.1% sqlite3 288504 288072 -0.1% 7zip-benchmark 573796 570768 -0.5% Geomean difference -0.1% Differential Revision: https://reviews.llvm.org/D105069
Extend the SetCurrentThread() method to support specifying an alternate PID to switch to. This makes it possible to issue requests to forked processes. Differential Revision: https://reviews.llvm.org/D100262
…or non-LP64. This broke ARM builds e.g.: https://lab.llvm.org/buildbot/#/builders/187/builds/212
For some reason we/I started writing these as returning bool when the return value is actually ignored by the combiner.
This patch fixes a failure in `TestFunctionStarts.py` that appeared following a change of implementation for synthetic symbol names: https://reviews.llvm.org/D105160 The failure is caused because the previously mentioned patch removes the object file basename from the generated synthetic symbol names to allow them to be shared in the constant string pool. Hence, that last check is not necessary anymore. rdar://80092322 Differential Revision: https://reviews.llvm.org/D105366 Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
… terminator These rely on the fact that currently simplifycfg won't really propagate said `unreachable`, but that is about to change.
…pad-split.ll It is being affected by an upcoming SimplifyCFG change.
gtest highly recommends this prefix, and runs death tests first (https://github.com/google/googletest/blob/master/docs/advanced.md#death-test-naming). This may help with some spurious bot failures like https://lab.llvm.org/buildbot/#/builders/169/builds/1290/steps/25/logs/stdio. Reviewed By: cryptoad, vitalybuka Differential Revision: https://reviews.llvm.org/D105371
The implementation has become too unwieldy and cognitive overhead wins. Instead compress the implementation in preparation for additional lowering paths. This is a resubmit of https://reviews.llvm.org/D105359 without ordering ambiguities. Differential Revision: https://reviews.llvm.org/D105367
Allow a preprocessor observer to be notified of mark pragmas. Although this does not impact code generation in any way, it is useful for other clients, such as clangd, to be able to identify any marked regions. Reviewed By: dgoldman Differential Revision: https://reviews.llvm.org/D105368
This revision extends the sparse compiler support from fp/int addition and multiplication to fp/int negation and subtraction, thereby increasing the scope of sparse kernels that can be compiled. Reviewed By: gussmith23 Differential Revision: https://reviews.llvm.org/D105306
This reverts commit 8cd35ad. It breaks `TestMembersAndLocalsWithSameName.py` on GreenDragon and Mikael Holmén points out in D104827 that bitcode files created with the patch cannot be parsed with binaries built before it.
D74751 added `ClearDSOLocalOnDeclarations` and dropped dso_local for isDeclarationForLinker `GlobalValue`s. It missed a case for imported declarations (`doImportAsDefinition` is false while `isPerformingImport` is true). This can lead to a linker error for a default visibility symbol in `ld.lld -shared`. When `ClearDSOLocalOnDeclarations` is true, we check `isPerformingImport() && !doImportAsDefinition(&GV)` along with `GV.isDeclarationForLinker()`. The new condition checks an imported declaration. This patch fixes a `LLVMPolly.so` link error using a trunk clang -DLLVM_ENABLE_LTO=Thin. Reviewed By: tejohnson Differential Revision: https://reviews.llvm.org/D104986
…dScatter from VT to MemVT. Use getMemoryVT() in MGATHER/MSCATTER DAG combines instead of using the passthru or store value VT for this argument.
Allocate non-volatile registers in order to be compatible with ABI, regarding gpr_save. Quoted from https://www.ibm.com/docs/en/ssw_aix_72/assembler/assembler_pdf.pdf page55, > The preferred method of using GPRs is to use the volatile registers first. Next, use the nonvolatile registers > in descending order, starting with GPR31. This patch is based on @jsji 's initial draft. Tested on test-suite and SPEC, found no degradation. Reviewed By: jsji, ZarkoCA, xingxue Differential Revision: https://reviews.llvm.org/D100167
This adds simple patterns for signed and unsigned saturating extract narrow instructions. They combine a min/max/truncate into a single instruction, providing that the immediates on the min/max are correct for the saturation type. This is just handled in tablegen with some extra patterns. v2i64->v2i32 is not handled here as the min/max nodes are not legal, making the lowering quite different. Differential Revision: https://reviews.llvm.org/D103263
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