The verilog code for MIPS based 32 bit RISC processor with thermal management unit and flexible 5 stage pipelining is implemented. The pipeline is made flexible to switch in between 4 stage and 5 stage with respect to instruction type. Thus by reducing the data dependancy the processing time is reduced. The Thermal managemant unit with dynamic frequency scaling is used for thermal stability of hardware.
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The verilog code for MIPS based 32 bit RISC processor with thermal management unit and flexible 5 stage pipelining is implemented.
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