cursed names but they fit in the table better IM SORRY

xubiod · Mar 7, 2024 · d2537a0 · d2537a0
1 parent 88f2384
commit d2537a0
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Showing 3 changed files with 36 additions and 36 deletions.
diff --git a/cpu/core.go b/cpu/core.go
@@ -269,41 +269,41 @@ func (c *Core) prepare() {
 	}
 
 	c.execMapByteCMOS = map[byte]func(uint8){
-		0x04: c.TSB__ZPg, 0x07: c.RMB__Gen(0),
-		0x12: c.ORA__IZP, 0x14: c.TRB__ZPg, 0x17: c.RMB__Gen(1),
-		0x27: c.RMB__Gen(2),
-		0x32: c.AND__IZP, 0x34: c.BIT__ZPx, 0x37: c.RMB__Gen(3),
-		0x47: c.RMB__Gen(4),
-		0x52: c.EOR__IZP, 0x57: c.RMB__Gen(5),
-		0x64: c.STZ__ZPg, 0x67: c.RMB__Gen(6),
-		0x72: c.ADC__IZP, 0x74: c.STZ__ZPx, 0x77: c.RMB__Gen(7),
-		0x80: c.BRA__rel, 0x87: c.SMB__Gen(0), 0x89: c.BIT__Imm,
-		0x92: c.STA__IZP, 0x97: c.SMB__Gen(1),
-		0xA7: c.SMB__Gen(2),
-		0xB2: c.LDA__IZP, 0xB7: c.SMB__Gen(3),
-		0xC7: c.SMB__Gen(4),
-		0xD2: c.CMP__IZP, 0xD7: c.SMB__Gen(5),
-		0xE7: c.SMB__Gen(6),
-		0xF2: c.SBC__IZP, 0xF7: c.SMB__Gen(7),
+		0x04: c.TSB__ZPg, 0x07: c.RMB_G(0),
+		0x12: c.ORA__IZP, 0x14: c.TRB__ZPg, 0x17: c.RMB_G(1),
+		0x27: c.RMB_G(2),
+		0x32: c.AND__IZP, 0x34: c.BIT__ZPx, 0x37: c.RMB_G(3),
+		0x47: c.RMB_G(4),
+		0x52: c.EOR__IZP, 0x57: c.RMB_G(5),
+		0x64: c.STZ__ZPg, 0x67: c.RMB_G(6),
+		0x72: c.ADC__IZP, 0x74: c.STZ__ZPx, 0x77: c.RMB_G(7),
+		0x80: c.BRA__rel, 0x87: c.SMB_G(0), 0x89: c.BIT__Imm,
+		0x92: c.STA__IZP, 0x97: c.SMB_G(1),
+		0xA7: c.SMB_G(2),
+		0xB2: c.LDA__IZP, 0xB7: c.SMB_G(3),
+		0xC7: c.SMB_G(4),
+		0xD2: c.CMP__IZP, 0xD7: c.SMB_G(5),
+		0xE7: c.SMB_G(6),
+		0xF2: c.SBC__IZP, 0xF7: c.SMB_G(7),
 	}
 
 	c.execMapBitBranchCMOS = map[byte]func(uint8, uint8){
-		0x0F: c.BBR__Gen(0),
-		0x1F: c.BBR__Gen(1),
-		0x2F: c.BBR__Gen(2),
-		0x3F: c.BBR__Gen(3),
-		0x4F: c.BBR__Gen(4),
-		0x5F: c.BBR__Gen(5),
-		0x6F: c.BBR__Gen(6),
-		0x7F: c.BBR__Gen(7),
-		0x8F: c.BBS__Gen(0),
-		0x9F: c.BBS__Gen(1),
-		0xAF: c.BBS__Gen(2),
-		0xBF: c.BBS__Gen(3),
-		0xCF: c.BBS__Gen(4),
-		0xDF: c.BBS__Gen(5),
-		0xEF: c.BBS__Gen(6),
-		0xFF: c.BBS__Gen(7),
+		0x0F: c.BBR_G(0),
+		0x1F: c.BBR_G(1),
+		0x2F: c.BBR_G(2),
+		0x3F: c.BBR_G(3),
+		0x4F: c.BBR_G(4),
+		0x5F: c.BBR_G(5),
+		0x6F: c.BBR_G(6),
+		0x7F: c.BBR_G(7),
+		0x8F: c.BBS_G(0),
+		0x9F: c.BBS_G(1),
+		0xAF: c.BBS_G(2),
+		0xBF: c.BBS_G(3),
+		0xCF: c.BBS_G(4),
+		0xDF: c.BBS_G(5),
+		0xEF: c.BBS_G(6),
+		0xFF: c.BBS_G(7),
 	}
 
 	c.execMapShortCMOS = map[byte]func(uint16){

diff --git a/cpu/set_branch.go b/cpu/set_branch.go
@@ -92,7 +92,7 @@ func (c *Core) BRA__rel(raw uint8) {
 // this over and over
 //
 // CMOS 65c02
-func (c *Core) BBR__Gen(bit uint) func(zp byte, raw uint8) {
+func (c *Core) BBR_G(bit uint) func(zp byte, raw uint8) {
 	if bit > 7 {
 		panic("can only check bits from 0 to 7")
 	}
@@ -110,7 +110,7 @@ func (c *Core) BBR__Gen(bit uint) func(zp byte, raw uint8) {
 // this over and over
 //
 // CMOS 65c02
-func (c *Core) BBS__Gen(bit uint) func(zp byte, raw uint8) {
+func (c *Core) BBS_G(bit uint) func(zp byte, raw uint8) {
 	if bit > 7 {
 		panic("can only check bits from 0 to 7")
 	}

diff --git a/cpu/set_setclear.go b/cpu/set_setclear.go
@@ -29,7 +29,7 @@ func (c *Core) CLV____i() { c.PC += 1; c.Flags = c.Flags & ^FLAG_OVERFLOW }
 // this over and over
 //
 // CMOS 65c02
-func (c *Core) SMB__Gen(bit uint) func(zp byte) {
+func (c *Core) SMB_G(bit uint) func(zp byte) {
 	if bit > 7 {
 		panic("can only check bits from 0 to 7")
 	}
@@ -44,7 +44,7 @@ func (c *Core) SMB__Gen(bit uint) func(zp byte) {
 // this over and over
 //
 // CMOS 65c02
-func (c *Core) RMB__Gen(bit uint) func(zp byte) {
+func (c *Core) RMB_G(bit uint) func(zp byte) {
 	if bit > 7 {
 		panic("can only check bits from 0 to 7")
 	}