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va: jz4780: Follow-up to Ingenic video acceleration support
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Reverted disabling mipsr32r2 cause it leads to SIGILL in Android SKIA.
logcat error:
01-01 00:01:22.716  1083  1083 F libc    : Fatal signal 4 (SIGILL), code 128, fault addr 0x0 in tid 1083 (ndroid.systemui)
01-01 00:01:22.832    99    99 F DEBUG   : *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** ***
01-01 00:01:22.832    99    99 F DEBUG   : Build fingerprint: 'Android/aosp_ci20/ci20:6.0.1/MOB30D/alistair05241026:userdebug/test-keys'
01-01 00:01:22.832    99    99 F DEBUG   : Revision: '0'
01-01 00:01:22.832    99    99 F DEBUG   : ABI: 'mips'
01-01 00:01:22.833    99    99 F DEBUG   : pid: 1083, tid: 1083, name: ndroid.systemui  >>> com.android.systemui <<<
01-01 00:01:22.833    99    99 F DEBUG   : signal 4 (SIGILL), code 128 (SI_KERNEL), fault addr 0x0
01-01 00:01:22.864    99    99 F DEBUG   :  zr 00000000  at 00000001  v0 00000000  v1 00000001
01-01 00:01:22.864    99    99 E DEBUG   : AM write failed: Broken pipe
01-01 00:01:22.864    99    99 F DEBUG   :  a0 70cb8160  a1 70cb8160  a2 721f890c  a3 00000001
01-01 00:01:22.864    99    99 F DEBUG   :  t0 00000000  t1 7fa2fb30  t2 00000001  t3 00000000
01-01 00:01:22.865    99    99 F DEBUG   :  t4 00000001  t5 00000000  t6 00000001  t7 7fa2fce0
01-01 00:01:22.865    99    99 F DEBUG   :  s0 721f890c  s1 00000001  s2 00000002  s3 721f8924
01-01 00:01:22.865    99    99 F DEBUG   :  s4 00000000  s5 00000000  s6 766f3000  s7 00000000
01-01 00:01:22.865    99    99 F DEBUG   :  t8 766f3000  t9 766f6810  k0 73a76500  k1 00000000
01-01 00:01:22.865    99    99 F DEBUG   :  gp 76a20040  sp 7fa2fac0  s8 7fa2fce0  ra 766f89b8
01-01 00:01:22.865    99    99 F DEBUG   :  hi 00000000  lo 55555556 bva 721f8924 epc 766f8674
01-01 00:01:22.893    99    99 F DEBUG   :
01-01 00:01:22.893    99    99 F DEBUG   : backtrace:
01-01 00:01:22.893    99    99 F DEBUG   :     #00 pc 00215674  /system/lib/libskia.so (SkOpSpan::sortableTop(SkOpContour*)+1052)
01-01 00:01:22.893    99    99 F DEBUG   :     #1 pc 00215d68  /system/lib/libskia.so (SkOpSegment::findSortableTop(SkOpContour*)+112)
01-01 00:01:22.893    99    99 F DEBUG   :     #2 pc 00215e10  /system/lib/libskia.so (SkOpContour::findSortableTop(SkOpContour*)+72)
01-01 00:01:22.893    99    99 F DEBUG   :     #3 pc 00215e90  /system/lib/libskia.so (FindSortableTop(SkOpContourHead*)+88)
01-01 00:01:22.893    99    99 F DEBUG   :     #4 pc 001e1194  /system/lib/libskia.so (OpDebug(SkPath const&, SkPath const&, SkPathOp, SkPath*, bool)+868)
01-01 00:01:22.893    99    99 F DEBUG   :     #5 pc 001e1940  /system/lib/libskia.so (Op(SkPath const&, SkPath const&, SkPathOp, SkPath*)+44)
01-01 00:01:22.893    99    99 F DEBUG   :     #6 pc 33b8884c  /data/dalvik-cache/mips/system@framework@boot.oat (offset 0x215b000)

Ingenic introduced new cache driver in video acceleration support patch and disabled
selection if MIPS_CPU_SCACHE which was used earlier. Cache driver selection has been
provided in order to easily select between new and old cache driver in case that problems
are encountered in the future.

Enabled VPU support in ci20_android_defconfig.

Removed dummy functions and switch to the proper ones in drivers/staging/imgtec/ci20/

Change-Id: I399ea09bcd5454339260b9dfd942a87a19a3cfa2
Signed-off-by: Dragan Cecavac <dragan.cecavac@imgtec.com>
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@cecavac
cecavac committed Sep 19, 2016
1 parent c105dd5 commit 33e5302
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Showing 6 changed files with 19 additions and 52 deletions.
27 changes: 14 additions & 13 deletions arch/mips/Kconfig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -254,7 +254,7 @@ config MACH_JZ4740

config MACH_JZ4780
bool "Ingenic JZ4780 based machines"
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_ZBOOT_UART16550
Expand All @@ -272,7 +272,6 @@ config MACH_JZ4780
select USE_OF
select LIBFDT
select SYS_SUPPORTS_SMP
select CONFIG_XBURST_CACHE

config LANTIQ
bool "Lantiq based platforms"
Expand Down Expand Up @@ -351,7 +350,6 @@ config MIPS_MALTA
select I8253
select I8259
select MIPS_BONITO64
select MIPS_CPU_SCACHE
select PCI_GT64XXX_PCI0
select MIPS_MSC
select SWAP_IO_SPACE
Expand Down Expand Up @@ -1619,7 +1617,6 @@ config CPU_BMIPS4380

config CPU_BMIPS5000
bool
select MIPS_CPU_SCACHE
select SYS_SUPPORTS_SMP
select SYS_SUPPORTS_HOTPLUG_CPU

Expand Down Expand Up @@ -1930,14 +1927,22 @@ config IP22_CPU_SCACHE
bool
select BOARD_SCACHE

#
# Support for a MIPS32 / MIPS64 style S-caches
#
choice
prompt "Cache type"
default MIPS_CPU_SCACHE

config MIPS_CPU_SCACHE
bool
bool "Support for a MIPS32 / MIPS64 style S-caches"
depends on (CPU_BMIPS5000 || MACH_JZ4780 || MIPS_MALTA)
select BOARD_SCACHE
select MIPS_L1_CACHE_SHIFT_6

config XBURST_CACHE
bool "Support for Ingenic's Xburst cache"
depends on MACH_JZ4780

endchoice

config R5000_CPU_SCACHE
bool
select BOARD_SCACHE
Expand Down Expand Up @@ -1967,11 +1972,7 @@ config CPU_R4K_FPU

config CPU_R4K_CACHE_TLB
bool
default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON || MACH_JZ4780)

config XBURST_CACHE
bool
default y if (MACH_JZ4780)
default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON || (MACH_JZ4780 && XBURST_CACHE))

config MIPS_MT_SMP
bool "MIPS MT SMP support (1 TC on each available VPE)"
Expand Down
2 changes: 1 addition & 1 deletion arch/mips/configs/ci20_android_defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -198,6 +198,7 @@ CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_UID_STAT=y
CONFIG_JZ_VPU=y
CONFIG_EEPROM_INGENIC=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
Expand Down Expand Up @@ -436,7 +437,6 @@ CONFIG_PROC_KCORE=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CONFIGFS_FS=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_PSTORE=y
Expand Down
2 changes: 1 addition & 1 deletion arch/mips/include/asm/mach-jz4740/jz4780/cpu-feature-overrides.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_pindexed_dcache 0
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 0
#define cpu_has_mips32r2 1
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_dsp 0
Expand Down
2 changes: 1 addition & 1 deletion arch/mips/include/asm/rjzcache.h
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Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ do { \
do { \
unsigned long tmp; \
__asm__ __volatile__( \
".set mips32\n\t" \
".set mips32r2\n\t" \
"mfc0 %0, $16, 7\n\t" \
"nop\n\t" \
"ori %0, 2\n\t" \
Expand Down
7 changes: 2 additions & 5 deletions drivers/staging/imgtec/ci20/syslocal.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -63,6 +63,8 @@ extern "C" {

#include <linux/platform_device.h>

#include<dt-bindings/clock/jzcpm_pwc.h>

#define PVR_XB47_TIMING_CPM

#if !defined(NO_HARDWARE) && \
Expand Down Expand Up @@ -146,11 +148,6 @@ PVRSRV_ERROR SysDvfsDeinitialize(SYS_SPECIFIC_DATA *psSysSpecificData);

#define PWC_GPU "gpu"

void *cpm_pwc_get(char *name);
void cpm_pwc_put(void *handle);
int cpm_pwc_enable(void *handle);
int cpm_pwc_disable(void *handle);

#if defined(__cplusplus)
}
#endif
Expand Down
31 changes: 0 additions & 31 deletions drivers/staging/imgtec/ci20/sysutils.c
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Original file line number Diff line number Diff line change
Expand Up @@ -68,37 +68,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

extern struct platform_device *gpsPVRLDMDev;

/*
* Stubs for cpm_pwc_* functions present in the Linux 3.0.8 kernel, but not
* in 3.18.
*/

void *cpm_pwc_get(char *name)
{
(void) name;

return (void *)(uintptr_t)1;
}

void cpm_pwc_put(void *handle)
{
(void) handle;
}

int cpm_pwc_enable(void *handle)
{
(void) handle;

return 0;
}

int cpm_pwc_disable(void *handle)
{
(void) handle;

return 0;
}

static PVRSRV_ERROR PowerLockWrap(SYS_SPECIFIC_DATA *psSysSpecData, IMG_BOOL bTryLock)
{
if (!in_interrupt())
Expand Down

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