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Derive rtlil IsString, fixup tests
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@dopamane
dopamane committed Jun 4, 2024
1 parent f4fe638 commit 620b15d
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Showing 2 changed files with 72 additions and 65 deletions.
41 changes: 21 additions & 20 deletions src/Bayeux/Rtlil.hs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -65,11 +65,12 @@ module Bayeux.Rtlil
, UpdateStmt(..)
) where

import Data.String
import Data.Text (Text)
import Prettyprinter

newtype Ident = Ident Text
deriving (Eq, Pretty, Read, Show)
deriving (Eq, IsString, Pretty, Read, Show)

data Value = Value Integer [BinaryDigit]
deriving (Eq, Read, Show)
Expand Down Expand Up @@ -121,7 +122,7 @@ instance Pretty Module where
]

newtype ModuleStmt = ModuleStmt Ident
deriving (Eq, Read, Show)
deriving (Eq, IsString, Read, Show)

instance Pretty ModuleStmt where
pretty (ModuleStmt i) = "module" <+> pretty i <> hardline
Expand Down Expand Up @@ -206,7 +207,7 @@ instance Pretty WireStmt where
pretty (WireStmt os i) = "wire" <+> hsep (pretty <$> os) <+> pretty i <> hardline

newtype WireId = WireId Ident
deriving (Eq, Pretty, Read, Show)
deriving (Eq, IsString, Pretty, Read, Show)

data WireOption = WireOptionWidth Integer
| WireOptionOffset Integer
Expand Down Expand Up @@ -267,10 +268,10 @@ instance Pretty CellStmt where
pretty (CellStmt t i) = "cell" <+> pretty t <+> pretty i <> hardline

newtype CellId = CellId Ident
deriving (Eq, Pretty, Read, Show)
deriving (Eq, IsString, Pretty, Read, Show)

newtype CellType = CellType Ident
deriving (Eq, Pretty, Read, Show)
deriving (Eq, IsString, Pretty, Read, Show)

data ParamType = Signed | Real
deriving (Eq, Read, Show)
Expand All @@ -297,20 +298,20 @@ instance Pretty CellEndStmt where

sbRgbaDrv :: Cell
sbRgbaDrv = Cell
[AttrStmt (Ident "\\module_not_derived") $ ConstantInteger 1]
(CellStmt (CellType $ Ident "\\SB_RGBA_DRV") (CellId $ Ident "\\RGBA_DRIVER"))
[ CellParameter Nothing (Ident "\\CURRENT_MODE") $ ConstantString "0b1"
, CellParameter Nothing (Ident "\\RGB0_CURRENT") $ ConstantString "0b111111"
, CellParameter Nothing (Ident "\\RGB1_CURRENT") $ ConstantString "0b111111"
, CellParameter Nothing (Ident "\\RGB2_CURRENT") $ ConstantString "0b111111"
, CellConnect (Ident "\\CURREN") $ SigSpecConstant $ ConstantValue $ Value 1 [B1]
, CellConnect (Ident "\\RGB0") $ SigSpecWireId $ WireId $ Ident "\\red"
, CellConnect (Ident "\\RGB0PWM") $ SigSpecWireId $ WireId $ Ident "\\pwm_r"
, CellConnect (Ident "\\RGB1") $ SigSpecWireId $ WireId $ Ident "\\green"
, CellConnect (Ident "\\RGB1PWM") $ SigSpecWireId $ WireId $ Ident "\\pwm_g"
, CellConnect (Ident "\\RGB2") $ SigSpecWireId $ WireId $ Ident "\\blue"
, CellConnect (Ident "\\RGB2PWM") $ SigSpecWireId $ WireId $ Ident "\\pwm_b"
, CellConnect (Ident "\\RGBLEDEN") $ SigSpecConstant $ ConstantValue $ Value 1 [B1]
[AttrStmt "\\module_not_derived" $ ConstantInteger 1]
(CellStmt "\\SB_RGBA_DRV" "\\RGBA_DRIVER")
[ CellParameter Nothing "\\CURRENT_MODE" $ ConstantString "0b1"
, CellParameter Nothing "\\RGB0_CURRENT" $ ConstantString "0b111111"
, CellParameter Nothing "\\RGB1_CURRENT" $ ConstantString "0b111111"
, CellParameter Nothing "\\RGB2_CURRENT" $ ConstantString "0b111111"
, CellConnect "\\CURREN" $ SigSpecConstant $ ConstantValue $ Value 1 [B1]
, CellConnect "\\RGB0" $ SigSpecWireId "\\red"
, CellConnect "\\RGB0PWM" $ SigSpecWireId "\\pwm_r"
, CellConnect "\\RGB1" $ SigSpecWireId "\\green"
, CellConnect "\\RGB1PWM" $ SigSpecWireId "\\pwm_g"
, CellConnect "\\RGB2" $ SigSpecWireId "\\blue"
, CellConnect "\\RGB2PWM" $ SigSpecWireId "\\pwm_b"
, CellConnect "\\RGBLEDEN" $ SigSpecConstant $ ConstantValue $ Value 1 [B1]
]
CellEndStmt

Expand All @@ -325,7 +326,7 @@ instance Pretty Process where
]

newtype ProcStmt = ProcStmt Ident
deriving (Eq, Read, Show)
deriving (Eq, IsString, Read, Show)

instance Pretty ProcStmt where
pretty (ProcStmt i) = "process" <+> pretty i <> hardline
Expand Down
96 changes: 51 additions & 45 deletions test/Test/Bayeux/Rtlil.hs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,95 +21,101 @@ import Test.Tasty.Golden

tests :: [TestTree]
tests =
[ goldenVsString "pretty-led" (curDir </> "pretty-led" <.> "golden") $ return $
fromString $ T.unpack $ render $ pretty rtlilLed
[ testGroup "pretty"
[ prettyTest "led" rtlilLed
, prettyTest "sbRgbaDrv" sbRgbaDrv
]
, testCase "synth-led" $ withTempFile $ \f -> do
TIO.writeFile f $ render $ pretty rtlilLed
let c = "yosys -q -p \"synth_ice40\" -f rtlil " <> f
(ExitSuccess @=?) =<< waitForProcess =<< spawnCommand c
, goldenVsString "pretty-sbRgbaDrv" (curDir </> "pretty-sbRgbaDrv" <.> "golden") $ return $
fromString $ T.unpack $ render $ pretty sbRgbaDrv
]

prettyTest :: Pretty a => TestName -> a -> TestTree
prettyTest n = goldenVsString n (curDir </> n' <.> "golden")
. return . fromString . T.unpack . render . pretty
where
n' = "pretty-" <> n

curDir :: FilePath
curDir = "test" </> "Test" </> "Bayeux" </> "Rtlil"

rtlilLed :: File
rtlilLed = File Nothing
[ Module
[]
(ModuleStmt $ Ident "\\top")
[ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionInput 1] $ WireId $ Ident "\\clk"
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionOutput 2] $ WireId $ Ident "\\LED_R"
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionOutput 3] $ WireId $ Ident "\\LED_G"
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionOutput 4] $ WireId $ Ident "\\LED_B"
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth 26] $ WireId $ Ident "\\counter"
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth 32] $ WireId $ Ident "\\counter_plus_one"
"\\top"
[ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionInput 1] "\\clk"
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionOutput 2] "\\LED_R"
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionOutput 3] "\\LED_G"
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionOutput 4] "\\LED_B"
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth 26] "\\counter"
, ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth 32] "\\counter_plus_one"
, ModuleBodyCell $ Cell
[]
(CellStmt (CellType $ Ident "$add") (CellId $ Ident "$increment"))
[ CellParameter Nothing (Ident "\\A_SIGNED") $ ConstantInteger 0
, CellParameter Nothing (Ident "\\A_WIDTH") $ ConstantInteger 26
, CellParameter Nothing (Ident "\\B_SIGNED") $ ConstantInteger 0
, CellParameter Nothing (Ident "\\B_WIDTH") $ ConstantInteger 32
, CellParameter Nothing (Ident "\\Y_WIDTH") $ ConstantInteger 32
, CellConnect (Ident "\\A") $ SigSpecWireId $ WireId $ Ident "\\counter"
, CellConnect (Ident "\\B") $ SigSpecConstant $ ConstantInteger 1
, CellConnect (Ident "\\Y") $ SigSpecWireId $ WireId $ Ident "\\counter_plus_one"
(CellStmt "$add" "$increment")
[ CellParameter Nothing "\\A_SIGNED" $ ConstantInteger 0
, CellParameter Nothing "\\A_WIDTH" $ ConstantInteger 26
, CellParameter Nothing "\\B_SIGNED" $ ConstantInteger 0
, CellParameter Nothing "\\B_WIDTH" $ ConstantInteger 32
, CellParameter Nothing "\\Y_WIDTH" $ ConstantInteger 32
, CellConnect "\\A" $ SigSpecWireId "\\counter"
, CellConnect "\\B" $ SigSpecConstant $ ConstantInteger 1
, CellConnect "\\Y" $ SigSpecWireId "\\counter_plus_one"
]
CellEndStmt
, ModuleBodyCell $ Cell
[]
(CellStmt (CellType $ Ident "$not") (CellId $ Ident "$not$1"))
[ CellParameter Nothing (Ident "\\A_SIGNED") $ ConstantInteger 0
, CellParameter Nothing (Ident "\\A_WIDTH") $ ConstantInteger 1
, CellParameter Nothing (Ident "\\Y_WIDTH") $ ConstantInteger 1
, CellConnect (Ident "\\A") $ SigSpecSlice
(SigSpecWireId $ WireId $ Ident "\\counter")
(CellStmt "$not" "$not$1")
[ CellParameter Nothing "\\A_SIGNED" $ ConstantInteger 0
, CellParameter Nothing "\\A_WIDTH" $ ConstantInteger 1
, CellParameter Nothing "\\Y_WIDTH" $ ConstantInteger 1
, CellConnect "\\A" $ SigSpecSlice
(SigSpecWireId "\\counter")
23
Nothing
, CellConnect (Ident "\\Y") $ SigSpecWireId $ WireId $ Ident "\\LED_R"
, CellConnect "\\Y" $ SigSpecWireId "\\LED_R"
]
CellEndStmt
, ModuleBodyCell $ Cell
[]
(CellStmt (CellType $ Ident "$not") (CellId $ Ident "$not$2"))
[ CellParameter Nothing (Ident "\\A_SIGNED") $ ConstantInteger 0
, CellParameter Nothing (Ident "\\A_WIDTH") $ ConstantInteger 1
, CellParameter Nothing (Ident "\\Y_WIDTH") $ ConstantInteger 1
, CellConnect (Ident "\\A") $ SigSpecSlice
(SigSpecWireId $ WireId $ Ident "\\counter")
(CellStmt "$not" "$not$2")
[ CellParameter Nothing "\\A_SIGNED" $ ConstantInteger 0
, CellParameter Nothing "\\A_WIDTH" $ ConstantInteger 1
, CellParameter Nothing "\\Y_WIDTH" $ ConstantInteger 1
, CellConnect "\\A" $ SigSpecSlice
(SigSpecWireId "\\counter")
24
Nothing
, CellConnect (Ident "\\Y") $ SigSpecWireId $ WireId $ Ident "\\LED_G"
, CellConnect "\\Y" $ SigSpecWireId "\\LED_G"
]
CellEndStmt
, ModuleBodyCell $ Cell
[]
(CellStmt (CellType $ Ident "$not") (CellId $ Ident "$not$3"))
[ CellParameter Nothing (Ident "\\A_SIGNED") $ ConstantInteger 0
, CellParameter Nothing (Ident "\\A_WIDTH") $ ConstantInteger 1
, CellParameter Nothing (Ident "\\Y_WIDTH") $ ConstantInteger 1
, CellConnect (Ident "\\A") $ SigSpecSlice
(SigSpecWireId $ WireId $ Ident "\\counter")
(CellStmt "$not" "$not$3")
[ CellParameter Nothing "\\A_SIGNED" $ ConstantInteger 0
, CellParameter Nothing "\\A_WIDTH" $ ConstantInteger 1
, CellParameter Nothing "\\Y_WIDTH" $ ConstantInteger 1
, CellConnect "\\A" $ SigSpecSlice
(SigSpecWireId "\\counter")
25
Nothing
, CellConnect (Ident "\\Y") $ SigSpecWireId $ WireId $ Ident "\\LED_B"
, CellConnect "\\Y" $ SigSpecWireId "\\LED_B"
]
CellEndStmt
, ModuleBodyProcess $ Process
[]
(ProcStmt $ Ident "$run")
"$run"
(ProcessBody
[]
Nothing
[]
[ Sync
(SyncStmt Posedge (SigSpecWireId $ WireId $ Ident "\\clk"))
(SyncStmt Posedge (SigSpecWireId "\\clk"))
[ UpdateStmt
(DestSigSpec $ SigSpecWireId $ WireId $ Ident "\\counter")
(DestSigSpec $ SigSpecWireId "\\counter")
(SrcSigSpec $ SigSpecSlice
(SigSpecWireId $ WireId $ Ident "\\counter_plus_one")
(SigSpecWireId "\\counter_plus_one")
25
(Just 0)
)
Expand Down

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